US5032801A
Expired / Lapsed
US
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High performance attenuator configuration
Assignee: Tektronix Inc
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Filing: 1990-07-31
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Granted: 1991-07-16
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Expires: 2010-07-31
Abstract
Abstract A high performance attenuator configuration divides a signal path into a plurality of parallel attenuator paths, each path having a predetermined attenuation value. A switch for each attenuator path is provided to couple selectively one of the attenuator paths to an input connector. Each attenuator path has an FET buffer amplifier, and the outputs of the FET buffer amplifiers are input to an electronic switch or multiplexer. The electronic switch selects the FET buffer amplifier output to be passed on to an output drive circuit.
Inventors
- 👤 James Woo
- 👤 Marvin E. Lavoie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 14:36
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/24; H03H11/245
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
54 words
An attenuator circuit comprising: a plurality of parallel paths, each path providing a different predetermined amount of attenuation; separate means in each separate parallel path for coupling an input signal to a selected one of the parallel paths; and means for electronically switching the selected one of the parallel paths to an output driver.
Claim 2
Dependent Claim
54 words
An attenuator circuit comprising: a plurality of parallel paths, each path providing a different predetermined amount of attenuation; separate means in each separate parallel path for coupling an input signal to a selected one of the parallel paths; and means for electronically switching the selected one of the parallel paths to an output driver.
Claim 3
Dependent Claim
74 words
An attenuator circuit as recited in claim 1 wherein the switching means comprises: a plurality of switch transistors, one for each parallel path, each switch transistor being selectively coupled with the output driver to form a unity gain feedback amplifier that has a high input impedance and a low output impedance; and means for selecting one of the switch transistors to be coupled with the output driver to form the unity gain feedback amplifier.
Claim 4
Dependent Claim
30 words
An attenuator circuit as recited in claim 2. wherein the switching means further comprises a buffer amplifier between each parallel path and the input terminal o the corresponding switch transistor.
Claim 5
Dependent Claim
69 words
An attenuator circuit as recited in claim 1 wherein the output driver comprises: an input transistor having a plurality of input terminals, each input terminal being coupled to a separate one of the parallel paths; and an output emitter-follower transistor coupled to the output terminal of the input transistor, the emitter of the output emitter-follower transistor being coupled to the control terminal of the input transistor to provide feedback.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-15 | 1995-01-14 | 1995-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-15 | 1999-01-14 | 1999-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-15 | 2003-01-14 | 2003-07-16 | $7700.00 | Window Closed / Lapsed |