US5032797A
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US
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Differential input stage having improved common mode rejection
Assignee: Motorola Solutions Inc
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Filing: 1990-09-04
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Granted: 1991-07-16
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Expires: 2010-09-04
Abstract
Abstract A differential input stage is provided having primary and secondary differential input transistors, wherein the secondary differential transistors operating in response to the same common mode input signal conduct equal currents as flowing through the primary differential transistors into a dual output current mirror for supplying the nominal current flowing in the primary differential transistors. Since the dual output current mirror is supplying the current flowing through the primary differential transistors, a differential to single-ended converter normally operating in response to differential currents flowing through the primary differential transistors does not conduct any incremental current induced by the common mode input signal, hence, there is no change in the output voltage thereof.
Inventors
- 👤 Dejan Mijuskovic
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:58
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45179; H03F3/45183; H03F3/30; H03F3/3001; H03F3/3022; H03F3/3023; H03F3/45479; H03F3/45632; H03F3/45695; H03F3/45699; H03F3/45717; H03F2203/00; H03F2203/45; H03F2203/45626
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
142 words
A differential input stage responsive to first and second input signals, comprising: current supply means having first and second outputs for providing first and second currents; first and second transistors each having a gate, a drain and a source, said gates being respectively coupled for receiving the first and second input signals, said sources being coupled to said first output of said current supply means; a current mirror circuit having an input and having first and second outputs for providing respective output currents, said first output being coupled to said drain of said first transistor, said second output being coupled to said drain of said second transistor; and first means coupled between said input of said current mirror circuit and said second output of said current supply means and responsive to the first and second input signals for conducting said second current.
Claim 2
Dependent Claim
142 words
A differential input stage responsive to first and second input signals, comprising: current supply means having first and second outputs for providing first and second currents; first and second transistors each having a gate, a drain and a source, said gates being respectively coupled for receiving the first and second input signals, said sources being coupled to said first output of said current supply means; a current mirror circuit having an input and having first and second outputs for providing respective output currents, said first output being coupled to said drain of said first transistor, said second output being coupled to said drain of said second transistor; and first means coupled between said input of said current mirror circuit and said second output of said current supply means and responsive to the first and second input signals for conducting said second current.
Claim 3
Dependent Claim
139 words
The differential input stage of claim 1 wherein said current mirror circuit includes: a third transistor having a gate, a drain and a source, said source being coupled to a first source of operating potential, said gate and drain being coupled together to said input of said current mirror circuit; a fourth transistor having a gate, a drain and a source, said source being coupled to said first source of operating potential, said drain being coupled to said drain of said first transistor, said gate being coupled to said gate of said third transistor; and a fifth transistor having a gate, a drain and a source, said source being coupled to said first source of operating potential, said drain being coupled to said drain of said second transistor, said gate being coupled to said gate of said third transistor.
Claim 4
Dependent Claim
57 words
The differential input stage of claim 2 wherein said first means includes a sixth transistor having a gate, a drain and a source, said drain being coupled to said drain of said third transistor, said source being coupled to said second output of said current supply means, said gate being coupled for receiving the first input signal.
Claim 5
Dependent Claim
58 words
The differential input stage of claim 3 wherein said first means further includes a seventh transistor having a gate, a drain and a source, said drain being coupled to said drain of said third transistor, said source being coupled to said second output of said current supply means, said gate being coupled for receiving the second input signal.
Claim 6
Dependent Claim
102 words
The differential input stage of claim 4 wherein said current supply means includes: an eighth transistor having a gate, a drain and a source, said drain being coupled to said sources of said first and second transistors, said gate being coupled for receiving a bias potential, said source being coupled to a second source of operating potential; and a ninth transistor having a gate, a drain and a source, said drain being coupled to said sources of said sixth and seventh transistors, said gate being coupled for receiving said bias potential, said source being coupled to said second source of operating potential.
Claim 7
Dependent Claim
159 words
A differential input stage responsive to first and second input signals, comprising: current supply means having an output for providing a first current; first and second transistors each having a gate, a drain and a source, said gate of said first transistor being coupled for receiving the first input signal, said gate of said second transistor being coupled for receiving the second input signal, said sources being coupled to said output of said current supply means; a current mirror circuit having an input and having first and second outputs, said first output being coupled to said drain of said first transistor, said second output being coupled to said drain of said second transistor; and a third transistor having a gate, a drain and a source, said drain being coupled to said input of said current mirror circuit, said source being coupled to said output of said current supply means, said gate being coupled for receiving the first input signal.
Claim 8
Dependent Claim
159 words
A differential input stage responsive to first and second input signals, comprising: current supply means having an output for providing a first current; first and second transistors each having a gate, a drain and a source, said gate of said first transistor being coupled for receiving the first input signal, said gate of said second transistor being coupled for receiving the second input signal, said sources being coupled to said output of said current supply means; a current mirror circuit having an input and having first and second outputs, said first output being coupled to said drain of said first transistor, said second output being coupled to said drain of said second transistor; and a third transistor having a gate, a drain and a source, said drain being coupled to said input of said current mirror circuit, said source being coupled to said output of said current supply means, said gate being coupled for receiving the first input signal.
Claim 9
Dependent Claim
138 words
The differential input stage of claim 6 wherein said current mirror circuit includes: a fourth transistor having a gate, a drain and a source, said source being coupled to a first source of operating potential, said gate and drain being coupled together to said drain of said third transistor; a fifth transistor having a gate, a drain and a source, said source being coupled to said first source of operating potential, said drain being coupled to said drain of said first transistor, said gate being coupled to said gate of said fourth transistor; and a sixth transistor having a gate, a drain and a source, said source being coupled to said first source of operating potential, said drain being coupled to said drain of said second transistor, said gate being coupled to said gate of said fourth transistor.
Claim 10
Dependent Claim
53 words
The differential input stage of claim 7 further includes a seventh transistor having a gate, a drain and a source, said drain being coupled to said drain of said fourth transistor, said source being coupled to said output of said current supply means, said gate being coupled for receiving the second input signal.
Claim 11
Dependent Claim
59 words
The differential input stage of claim 8 wherein said current supply means includes an eighth transistor having a gate, a drain and a source, said drain being coupled to said sources of said first, second, third and seventh transistors, said gate being coupled for receiving a bias potential, said source being coupled to a second source of operating potential.
Claim 12
Dependent Claim
158 words
An integrated differential input circuit responsive to first and second input signals, comprising: current supply means having first and second outputs for providing first and second currents; first and second transistors each having a gate, a drain and a source, said gate of said first transistor being coupled for receiving the first input signal, said gate of said second transistor being coupled for receiving the second input signal, said sources being coupled to said first output of said current supply means; a current mirror circuit having an input and having first and second outputs for providing respective output currents, said first output being coupled to said drain of said first transistor, said second output being coupled to said drain of said second transistor; and first means coupled between said input of said current mirror circuit and said second output of said current supply means and responsive to the first and second input signals for conducting said second current.
Claim 13
Dependent Claim
158 words
An integrated differential input circuit responsive to first and second input signals, comprising: current supply means having first and second outputs for providing first and second currents; first and second transistors each having a gate, a drain and a source, said gate of said first transistor being coupled for receiving the first input signal, said gate of said second transistor being coupled for receiving the second input signal, said sources being coupled to said first output of said current supply means; a current mirror circuit having an input and having first and second outputs for providing respective output currents, said first output being coupled to said drain of said first transistor, said second output being coupled to said drain of said second transistor; and first means coupled between said input of said current mirror circuit and said second output of said current supply means and responsive to the first and second input signals for conducting said second current.
Claim 14
Dependent Claim
139 words
The differential input circuit of claim 10 wherein said current mirror circuit includes: a third transistor having a gate, a drain and a source, said source being coupled to a first source of operating potential, said gate and drain being coupled together to said input of said current mirror circuit; a fourth transistor having a gate, a drain and a source, said source being coupled to said first source of operating potential, said drain being coupled to said drain of said first transistor, said gate being coupled to said gate of said third transistor; and a fifth transistor having a gate, a drain and a source, said source being coupled to said first source of operating potential, said drain being coupled to said drain of said second transistor, said gate being coupled to said gate of said third transistor.
Claim 15
Dependent Claim
57 words
The differential input stage of claim 11 wherein said first means includes a sixth transistor having a gate, a drain and a source, said drain being coupled to said drain of said third transistor, said source being coupled to said second output of said current supply means, said gate being coupled for receiving the first input signal.
Claim 16
Dependent Claim
58 words
The differential input stage of claim 12 wherein said first means further includes a seventh transistor having a gate, a drain and a source, said drain being coupled to said drain of said third transistor, said source being coupled to said second output of said current supply means, said gate being coupled for receiving the second input signal.
Claim 17
Dependent Claim
102 words
The differential input stage of claim 13 wherein said current supply means includes: an eighth transistor having a gate, a drain and a source, said drain being coupled to said sources of said first and second transistors, said gate being coupled for receiving a bias potential, said source being coupled to a second source of operating potential; and a ninth transistor having a gate, a drain and a source, said drain being coupled to said sources of said sixth and seventh transistors, said gate being coupled for receiving said bias potential, said source being coupled to said second source of operating potential.
Claim 18
Independent Claim
127 words
A method of providing common mode rejection through a differential input stage, comprising the steps of: receiving first and second common mode input signals at the control inputs of first and second differentially coupled transistors of the differential input stage; conducting first and second currents through said first and second differentially coupled transistors respectively; detecting variation in said first and second currents induced by said first and second common mode input signals; supplying a third current having a similar variation as detected in said first and second currents; and mirroring the variation of said third current into both conduction paths of said first and second differentially coupled transistors to compensate for the variation of said first and second currents flowing through first and second differentially coupled transistors.
Claim 19
Independent Claim
127 words
A method of providing common mode rejection through a differential input stage, comprising the steps of: receiving first and second common mode input signals at the control inputs of first and second differentially coupled transistors of the differential input stage; conducting first and second currents through said first and second differentially coupled transistors respectively; detecting variation in said first and second currents induced by said first and second common mode input signals; supplying a third current having a similar variation as detected in said first and second currents; and mirroring the variation of said third current into both conduction paths of said first and second differentially coupled transistors to compensate for the variation of said first and second currents flowing through first and second differentially coupled transistors.
References Cited (Backward Citations)
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Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-15 | 1995-01-14 | 1995-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-15 | 1999-01-14 | 1999-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-15 | 2003-01-14 | 2003-07-16 | $7700.00 | Window Closed / Lapsed |