US5031136A
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US
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Signed-digit arithmetic processing units with binary operands
Assignee: Panasonic Holdings Corp
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Filing: 1990-05-07
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Granted: 1991-07-09
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Expires: 2010-05-07
Abstract
Abstract A high speed arithmetic processor includes an array of arithmetic cells which operate on digits internally represented in a signed-digit binary format. Certain of these cells perform subtraction operations on two ordinary binary digits, and produce the difference in a 2-bit signed-digit binary format, without requiring a separate ordinary binary to signed-digit binary converter.
Inventors
- 👤 Tamotsu Nishiyama
- 👤 Shigeo Kuninobu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 10:20
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/4824; G06F7/52; G06F7/523; G06F7/533; G06F7/5334; G06F7/5336; G06F7/5338; G06F7/535; G06F7/537; G06F7/5375
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
160 words
An arithmetic processing unit comprising: a) a plurality of arithmetic circuits, the i th of which receives a 1-bit signal x i which represents the i th digit of a binary minuend and the logical negation Y i of 1-bit signal y i which represents the i th digit of a binary subtrahend as two inputs, and determines therefrom and outputs a 2-bit signal z i 1 and z i 2 , which represents the i th digit of the difference as a signed-digit binary number, where z.sub.i.sup.1 =x.sub.i +Y.sub.i, z.sub.i.sup.2 =x.sub.1 ·y.sub.i +x.sub.1 ·y.sub.i ; and b) a plurality of signed-digit binary adders, the i th of which receives said 2-bit signal z i 1 and z i 2 as one of two inputs, and outputs the i th digit of a second signed-digit binary number, wherein said plurality of arithmetic circuits perform both a subtraction and a conversion from an ordinary binary number to a signed-digit binary number.
Claim 2
Dependent Claim
160 words
An arithmetic processing unit comprising: a) a plurality of arithmetic circuits, the i th of which receives a 1-bit signal x i which represents the i th digit of a binary minuend and the logical negation Y i of 1-bit signal y i which represents the i th digit of a binary subtrahend as two inputs, and determines therefrom and outputs a 2-bit signal z i 1 and z i 2 , which represents the i th digit of the difference as a signed-digit binary number, where z.sub.i.sup.1 =x.sub.i +Y.sub.i, z.sub.i.sup.2 =x.sub.1 ·y.sub.i +x.sub.1 ·y.sub.i ; and b) a plurality of signed-digit binary adders, the i th of which receives said 2-bit signal z i 1 and z i 2 as one of two inputs, and outputs the i th digit of a second signed-digit binary number, wherein said plurality of arithmetic circuits perform both a subtraction and a conversion from an ordinary binary number to a signed-digit binary number.
Claim 3
Dependent Claim
156 words
An arithmetic processing unit comprising: a) a plurality of arithmetic circuits, the i th of which receives a 1-bit signal x i which represents the i th digit of a binary minuend and a 1-bit signal y i which represents the i th digit of a binary subtrahend as two inputs, and determines therefrom and outputs a 2-bit signal z i 1 and z i 2 , which represents the i th digit of the difference as a signed-digit binary number, where z.sub.i.sup.1 =x.sub.i +y.sub.i, z.sub.i.sup.2 =x.sub.i ·y.sub.i +x.sub.i ·y.sub.i ; and b) a plurality of signed-digit binary adders, the i th of which receives said 2-bit signal z i 1 and z i 2 as one of the two inputs, and outputs the i th digit of a second signed-digit binary number, wherein said plurality of arithmetic circuits perform both a subtraction and a conversion from an ordinary binary number to a signed-digit binary number.
Claim 4
Dependent Claim
156 words
An arithmetic processing unit comprising: a) a plurality of arithmetic circuits, the i th of which receives a 1-bit signal x i which represents the i th digit of a binary minuend and a 1-bit signal y i which represents the i th digit of a binary subtrahend as two inputs, and determines therefrom and outputs a 2-bit signal z i 1 and z i 2 , which represents the i th digit of the difference as a signed-digit binary number, where z.sub.i.sup.1 =x.sub.i +y.sub.i, z.sub.i.sup.2 =x.sub.i ·y.sub.i +x.sub.i ·y.sub.i ; and b) a plurality of signed-digit binary adders, the i th of which receives said 2-bit signal z i 1 and z i 2 as one of the two inputs, and outputs the i th digit of a second signed-digit binary number, wherein said plurality of arithmetic circuits perform both a subtraction and a conversion from an ordinary binary number to a signed-digit binary number.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-08 | 1995-01-07 | 1995-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-08 | 1999-01-07 | 1999-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-08 | 2003-01-07 | 2003-07-09 | $7700.00 | Window Closed / Lapsed |