Abstract A video system includes a scan converter for developing a progressively scanned display of video lines from a two field interlaced line system. A spatial array of six pixels convering two successive video lines is developed and gradients are determined between diagonally opposed pairs of pixels and a vertically opposed pair of pixels in the array. The interpolated pixel is developed by averaging the two pixels in the smallest of the gradients. A non-orthogonal display is developed by using horizontally interpolated pixels in the array developed by averaging successive pairs of real pixels, which introduces an offset of one-half pixel duration to the interpolated pixels. An adaptive peaking and noise coring circuit is included. Another spatial array of three line of pixels, both real and interpolated, is developed and a horizontal, a vertical and two diagonal gradients between pairs of pixels in the array are calculated. Logic circuitry and a maximum value decoder determine a peaking factor based upon the maximum gradient. A simplified adjustable noise coring circuit with symmetrical and asymmetrical peaking is also disclosed.
Inventors
👤 Khosro M. Rabii
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-11-09 17:44
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/21
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
104 words
A video processing circuit comprising: means for developing a video signal to be peaked; means for developing a peaking component for peaking said video signal; multiplier mans for multiplying said peaking component with a programmable peaking factor; means for developing the absolute value of said peaking component; means for applying a coring factor for removing a center portion of said peaking component; means for splitting said cored peaking component into two portions; further multiplier means for multiplying one of said portions with another programmable peaking factor to develop a processed peaking component; and means for combining said processed peaking component with said video signal.
Claim 2
Dependent Claim
104 words
A video processing circuit comprising: means for developing a video signal to be peaked; means for developing a peaking component for peaking said video signal; multiplier mans for multiplying said peaking component with a programmable peaking factor; means for developing the absolute value of said peaking component; means for applying a coring factor for removing a center portion of said peaking component; means for splitting said cored peaking component into two portions; further multiplier means for multiplying one of said portions with another programmable peaking factor to develop a processed peaking component; and means for combining said processed peaking component with said video signal.
Claim 3
Dependent Claim
55 words
The system of claim 1 wherein said peaking component is expressed as a digital word, the most significant bit of which indicates the polarity of said peaking component and further including: multiplexer means controlled by said most significant bit and having a pair of inputs supplied with said two portions of said peaking component, respectively.
Claim 4
Independent Claim
95 words
A method of processing a video signal comprising the steps of: developing a digital representation of said video signal; multiplying said digital representation by a first programmable peaking factor; developing the absolute value of said multiplied digital representation; applying a coring factor to said multiplied digital representation to develop a cored signal; developing opposite polarity portions of said cored signal; multiplying one of said portions by another programmable factor; multiplexing said portions in accordance with the polarity of said digital representation to develop a peaking component; and applying said peaking component to said video signal.
Claim 5
Independent Claim
95 words
A method of processing a video signal comprising the steps of: developing a digital representation of said video signal; multiplying said digital representation by a first programmable peaking factor; developing the absolute value of said multiplied digital representation; applying a coring factor to said multiplied digital representation to develop a cored signal; developing opposite polarity portions of said cored signal; multiplying one of said portions by another programmable factor; multiplexing said portions in accordance with the polarity of said digital representation to develop a peaking component; and applying said peaking component to said video signal.