Device to generate brilliance levels on a display screen

Claim 3

A device according to claim 1, wherein said screen is divided into a plurality of Z rectangles, each of which is identified by its order, and wherein said asynchronous clock means comprises means for providing for a generation of control voltages depending on the order of each rectangle, thereby enabling a static correction of homogeneity defects in said screen.

Claim 4

A device according to claim 1, further comprising transcoding means for receiving input binary codes containing information on the level of brilliance desired and information representing the zone of the screen considered, and for delivering binary codes introduced in said conversion means, thus enabling a dynamic correction of the homogeneity defects of said screen.

Claim 5

A device according to claim 1 wherein said conversion means comprise a code-voltage converter consisting of: M count-down devices; M voltage generators respectively connected to the output of said M count-down devices; M n-bit binary codes being injected simultaneously and respectively into said M count-down devices, each count-down device emitting a pulse at the xth pulse give by said asynchronous clock means, x being a whole number corresponding specifically to the binary code injected into said count-down device, said pulse being sent into the generator connected to said count-down device and causing the generation of a control voltage, said M binary codes being converted into M control voltages, and wherein said asynchronous clock means (11) comprises: a clock; a memory; an addressing circuit of said memory, connected to said clock; a shift register with X moments working at the frequency of said clock, the input of which is connected to said memory; an "AND" gate, the inputs of which are connected to the output of said register and to said clock; said addressing circuit sending orders, at the frequency of said clock, for successive readings of binary codes contained in said memory, said binary codes being delivered in the form of sequences of bits to said shift register, said register being shifted at the frequency of said clock, and said gate being capable of delivering, depending on the nature of the information coming from the shift register, a pulse constituting an output of said asynchronous clock means.

Claim 6

A device according to claim 2 wherein said asynchronous clock means comprise: a clock (14); a memory (12); an addressing circuit (16) of said memory, having a first input connected to said clock and a second input (20) for receiving the order of one of said rectangles; a shift register (13) with x moments working at the frequency of said clock, the input of which is connected to said memory; an "AND" gate (15), the inputs of which are connected to the output of said register and to said clock; said addressing circuit sending orders, at the frequency of said clock, for successive readings of selected binary codes, selected from said binary codes contained in said memory through the introduction of the order of a rectangle through said second input, said binary codes being delivered in the form of a sequence of bits to said shift register, said shift register being shifted at the frequency of said clock, and said gate being capable of delivering, according to the nature of the information coming from said shift register, pulse constituting an output of said asynchronous clock means.

Claim 7

A device according to claim 3 wherein said conversion means comprise a code-voltage converter consisting of: M count-down devices; M voltage generators respectively connected to the output of the M count-down devices; M n-bit binary codes being injected simultaneously and respectively into said M count-down devices, each count-down device emitting a pulse at the xth pulse given by the asynchronous clock means, x being a whole number corresponding specifically to the binary code introduced into said count-down device, said pulse being sent into the generator connected to said count-down device and causing the generation of a control voltage, said M binary codes being converted into M control voltages, and wherein said transcoding means consist of M circuits respectively connected to the inputs of said M count-down devices and each having a memory and its addressing circuit, each of said circuits: receiving said information on the desired level of brilliance in the form of (n-p), with 0<p<n, and said information representing the zone of the screen considered in the form of p bits; delivering n bits forming said binary code injected into the count-down unit connected to the set considered.

Claim 8

A device according to claim 2 comprising, inter alia transcoding means receiving input binary codes containing a piece of information on the desired level of brilliance, and a piece of information on the zone considered of the screen, said transcoding means delivering binary codes introduced into said conversion means, enabling a combination of a static correction and a dynamic correction of the homogeneity defects of the screen, each rectangle being divided into sub-rectangles each constituting said zone of the screen considered for the dynamic correction.