US5029136A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-speed DRAM sense amp with high noise immunity
Assignee: Texas Instruments Inc
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Filing: 1989-10-16
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Granted: 1991-07-02
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Expires: 2009-10-16
Abstract
Abstract A sense amplifier (10) has P channel transistors (38,48) connected between first and second nodes (34,44) of the sense amplifier and respective bitlines (12,14). The gates (42,52) of the P channel transistors (38,48) are connected to ground. As the voltage at one of the nodes (34 or 44) approaches ground voltage during the sensing operation, the bitline (12 or 14) is effectively disconnected from the sense amplifier (10) thereby increasing sensing speed while reducing noise between the bitline and the node.
Inventors
- 👤 Hiep V. Tran
- 👤 Hugh P. McAdams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:38
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C7/00; G11C7/06; G11C7/065
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
107 words
A sense amplifier for a semiconductor memory device for sensing a voltage imbalance between first and second sense nodes comprising: respective bitlines coupled to the first and second nodes; memory cells operatively connected to said bitlines; latching circuitry connected to the first and second nodes for pulling the first and second nodes towards predetermined high and low voltages corresponding to the orientation of the voltage imbalance between sense nodes; and isolating circuitry comprising P channel transistors connected between said nodes and respective bitlines for automatically isolating one of said bitlines from its respective node responsive to a voltage change at that node caused by said latching circuitry.
Claim 2
Dependent Claim
107 words
A sense amplifier for a semiconductor memory device for sensing a voltage imbalance between first and second sense nodes comprising: respective bitlines coupled to the first and second nodes; memory cells operatively connected to said bitlines; latching circuitry connected to the first and second nodes for pulling the first and second nodes towards predetermined high and low voltages corresponding to the orientation of the voltage imbalance between sense nodes; and isolating circuitry comprising P channel transistors connected between said nodes and respective bitlines for automatically isolating one of said bitlines from its respective node responsive to a voltage change at that node caused by said latching circuitry.
Claim 3
Dependent Claim
133 words
A semiconductor memory device including a sense amplifier for sensing a voltage imbalance between first and second sense nodes in the semiconductor memory device, the memory device comprising: respective bitlines coupled to the first and second sense nodes; memory cells operatively connected to said bit lines; latching circuitry connected to the first and second sense nodes for changing voltages on the first and second sense nodes towards predetermined high and low voltages corresponding to the orientation of the voltage imbalance between the first and second sense nodes; first and second grounded gate transistors for coupling the respective bitlines to the first and second sense nodes and for automatically isolating one of said bitlines from its respective sense node in response to the voltage change at that sense node caused by said latching circuitry.
Claim 4
Dependent Claim
133 words
A semiconductor memory device including a sense amplifier for sensing a voltage imbalance between first and second sense nodes in the semiconductor memory device, the memory device comprising: respective bitlines coupled to the first and second sense nodes; memory cells operatively connected to said bit lines; latching circuitry connected to the first and second sense nodes for changing voltages on the first and second sense nodes towards predetermined high and low voltages corresponding to the orientation of the voltage imbalance between the first and second sense nodes; first and second grounded gate transistors for coupling the respective bitlines to the first and second sense nodes and for automatically isolating one of said bitlines from its respective sense node in response to the voltage change at that sense node caused by said latching circuitry.
Claim 5
Dependent Claim
35 words
A sense amplifier, in accordance with claim 2, wherein the first and second grounded gate transistors are P channel transistors, each having its conduction channel connected between one of said nodes and its respective bitline.
Claim 6
Dependent Claim
54 words
A sense amplifier, in accordance with claim 3, wherein first and second N channel transistors are interconnected with the P channel transistors and circuitry for pulling voltage on the gates of the N channel transistors below said predetermined low voltage to enable conduction between the first and second sense nodes and the respective bitlines.
Claim 7
Dependent Claim
129 words
An integrated circuit dynamic random access memory arrangement comprising: a sense amplifier including first and second nodes; a first voltage limiting transistor having one end of its conduction path connected to the first node and having a gate electrode connected to a reference potential; a second voltage limiting transistor having one end of its conduction path connected to the second node and having a gate electrode connected to the reference potential; a first bitline coupled through the conduction path of the first voltage limiting transistor to the first node; a second bitline coupled through the conduction path of the second voltage limiting transistor to the second node; a first plurality of memory cells coupled to the first bitline; and at least one memory cell coupled to the second bitline.
Claim 8
Dependent Claim
129 words
An integrated circuit dynamic random access memory arrangement comprising: a sense amplifier including first and second nodes; a first voltage limiting transistor having one end of its conduction path connected to the first node and having a gate electrode connected to a reference potential; a second voltage limiting transistor having one end of its conduction path connected to the second node and having a gate electrode connected to the reference potential; a first bitline coupled through the conduction path of the first voltage limiting transistor to the first node; a second bitline coupled through the conduction path of the second voltage limiting transistor to the second node; a first plurality of memory cells coupled to the first bitline; and at least one memory cell coupled to the second bitline.
Claim 9
Dependent Claim
19 words
An integrated circuit dynamic random access memory arrangement, in accordance with claim 5, wherein the reference potential is ground.
Claim 10
Dependent Claim
36 words
An integrated circuit dynamic random access memory arrangement, in accordance with claim 5, wherein the conduction path of either the first or the second voltage limiting transistor automatically is disabled from conducting during each sensing operation.
References Cited (Backward Citations)
US4716320A
Cited
US4816706A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-01 | 1994-12-31 | 1995-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-01 | 1998-12-31 | 1999-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-01 | 2002-12-31 | 2003-07-02 | $7700.00 | Window Closed / Lapsed |