US5029134A
Expired / Lapsed
US
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Memory circuit with improved serial access circuit arrangement
Assignee: Micron Memory Japan Ltd
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Filing: 1989-01-27
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Granted: 1991-07-02
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Expires: 2009-01-27
Abstract
Abstract A memory circuit provided with an improved serial access port which can be operated continuously without interruption is disclosed. The memory circuit comprises a plurality of sets of bit lines, each set of bit lines having first and second bit lines, a plurality of sets of latch circuits, eahc set of latch circuits having first and second latch circuits, first means for sequentially deriving data stored in the first latch circuits, second means for sequentially deriving data stored in the second latch circuits, and a plurality of switch circuits, each of the switch circuits being connected between each set of bit lines and each set of latch circuits and selectively providing a signal path between one of the first and second bit lines and one of the first and second latch circuits.
Inventors
- 👤 Hiroshi Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:51
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/103; G11C7/1075
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
254 words
A semiconductor memory circuit comprising a plurality of bit line sets, a plurality of word lines intersecting with said bit lines, each of said but line sets having first and second bit lines, a plurality of memory cells connected to said word lines and said bit lines, a plurality of latch circuit sets each having first and second latch circuits, a plurality of switch circuits, each of said switch circuits being connected between each set of first and second bit lines and each set of first and second latch circuits and selectively providing a signal path between one of the first and second bit lines of the same set for one of said first and second latch circuits of the same set, each of said switch circuits includes a first transfer gate connected between the first bit line of the associated bit line set and a common node, a second transfer gate connected between said common node and the first latch circuit of the associated latch circuit set, a third transfer gate connected between the second bit line of the associated bit line set and said common node, and a fourth transfer gate connected between said common node and the second latch circuit of the same latch circuit set, control means for controlling said switch circuits simultaneously, first means coupled to said first latch circuits for sequentially deriving data stored in said first latch circuits, and second means coupled to said second latch circuits for sequentially deriving data stored in said second latch circuits.
Claim 2
Dependent Claim
254 words
A semiconductor memory circuit comprising a plurality of bit line sets, a plurality of word lines intersecting with said bit lines, each of said but line sets having first and second bit lines, a plurality of memory cells connected to said word lines and said bit lines, a plurality of latch circuit sets each having first and second latch circuits, a plurality of switch circuits, each of said switch circuits being connected between each set of first and second bit lines and each set of first and second latch circuits and selectively providing a signal path between one of the first and second bit lines of the same set for one of said first and second latch circuits of the same set, each of said switch circuits includes a first transfer gate connected between the first bit line of the associated bit line set and a common node, a second transfer gate connected between said common node and the first latch circuit of the associated latch circuit set, a third transfer gate connected between the second bit line of the associated bit line set and said common node, and a fourth transfer gate connected between said common node and the second latch circuit of the same latch circuit set, control means for controlling said switch circuits simultaneously, first means coupled to said first latch circuits for sequentially deriving data stored in said first latch circuits, and second means coupled to said second latch circuits for sequentially deriving data stored in said second latch circuits.
Claim 3
Dependent Claim
20 words
The semiconductor memory circuit according to claim 1, further comprising a row decoder for selecting one of said word lines.
Claim 4
Dependent Claim
26 words
The semiconductor memory circuit according to claim 1, further comprising third means for determining a start address location of one of said first and second means.
Claim 5
Dependent Claim
57 words
The semiconductor memory circuit according to claim 1, further comprising means for making one and the other of said first and third transfer gates in each said switch circuit conductive and non-conductive respectively, and means for making one and the other of said second and fourth transfer gates in each said switch circuit conductive and non-conductive, respectively.
Claim 6
Dependent Claim
48 words
The semiconductor memory according to claim 1, further comprising a common data line, a plurality of first selection gates connected between said first latch circuits and said common data line and a plurality of second selection gates connected between said second latch circuits and said common data line.
Claim 7
Dependent Claim
252 words
A semiconductor memory circuit comprising a plurality of bit line sets each having first and second bit lines, a plurality of word lines intersecting with said bit lines, a plurality of memory cells connected to said word lines and said bit lines, a plurality of latch circuit sets each having first and second latch circuits, a plurality of switch circuits, each of said switch circuits being connected between each set of first and second bit lines and each set of first and second latch circuits and selectively providing one of first to fourth signal paths, said first signal path being connected between the first bit line of the associated bit line set and the first latch circuit of the associated latch circuit set, said second signal path being connected between the second bit line of the associated bit line set and the first latch circuit of the associated latch circuit set, said third signal path being connected between the first bit line of the associated bit line set and the second latch circuit of the associated latch circuit set, said fourth signal path being connected between the second bit line of the associated bit line set and the second latch circuit of the associated latch circuit set, control means for controlling said switch circuit simultaneously, first means coupled to said first latch circuits for sequentially deriving data stored in said first latch circuits, and second means coupled to said second latch circuits for sequentially deriving data stored in said second latch circuits.
Claim 8
Dependent Claim
252 words
A semiconductor memory circuit comprising a plurality of bit line sets each having first and second bit lines, a plurality of word lines intersecting with said bit lines, a plurality of memory cells connected to said word lines and said bit lines, a plurality of latch circuit sets each having first and second latch circuits, a plurality of switch circuits, each of said switch circuits being connected between each set of first and second bit lines and each set of first and second latch circuits and selectively providing one of first to fourth signal paths, said first signal path being connected between the first bit line of the associated bit line set and the first latch circuit of the associated latch circuit set, said second signal path being connected between the second bit line of the associated bit line set and the first latch circuit of the associated latch circuit set, said third signal path being connected between the first bit line of the associated bit line set and the second latch circuit of the associated latch circuit set, said fourth signal path being connected between the second bit line of the associated bit line set and the second latch circuit of the associated latch circuit set, control means for controlling said switch circuit simultaneously, first means coupled to said first latch circuits for sequentially deriving data stored in said first latch circuits, and second means coupled to said second latch circuits for sequentially deriving data stored in said second latch circuits.
Claim 9
Dependent Claim
97 words
The semiconductor memory circuit according to claim 6, in which each of said switch circuits includes a first transfer gate connected between the first bit line of the associated bit line set and a common node, a second transfer gate connected between said common node and the first latch circuit of the associated latch circuit set, a third transfer gate connected between the second bit line of the associated bit line set and said common node, and a fourth transfer gate connected between said common node and the second latch circuit of the same latch circuit set.
References Cited (Backward Citations)
US4769789A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-01 | 1994-12-31 | 1995-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-01 | 1998-12-31 | 1999-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-01 | 2002-12-31 | 2003-07-02 | $7700.00 | Window Closed / Lapsed |