US5029006A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Video signal processing circuit capable of enlarging and displaying a picture
Assignee: Hitachi Ltd
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Filing: 1989-04-25
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Granted: 1991-07-02
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Expires: 2009-04-25
Abstract
Abstract A video signal processing circuit capable of enlarging and displaying a picture and adapted for use in an apparatus in which a desired picture is selected, and a video signal representative of the desired picture under interlaced scanning is received, stored in a memory and processed to provide an enlarged video signal, comprises includes a real signal/interpolated signal preparation circuit for preparing, from the stored video signal, new scanning lines for an image to be enlarged, and a memory processing circuit having switching control function to store an output signal of the real signal/interpolated signal preparation circuit in a memory, read the video signal out of the memory at a period different from a period at which the output signal is stored in the memory, and delay a read-out signal by one or more fields so that an enlarged signal is delivered.
Inventors
- 👤 Kenji Katsumata
- 👤 Shigeru Hirahata
- 👤 Masato Sugiyama
- 👤 Takaaki Matono
- 👤 Kazuo Ishikura
- 👤 Sunao Suzuki
- 👤 Kazuhiro Kaizaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:02
CPC Classifications
G; G06; G06T; G06T3/00; G06T3/40; G06T3/4007; H; H04; H04N; H04N21/00; H04N21/40; H04N21/43; H04N21/44; H04N21/4402; H04N21/440263; H04N5/00; H04N5/222; H04N5/262; H04N5/2628; H04N5/44; H04N7/00; H04N7/01; H04N7/0117; H04N7/012
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
186 words
A video signal processing circuit capable of enlarging and displaying a picture and adapted to store an quantized video signal at a predetermined period in a memory and perform enlarged display of an original image by changing the period at which the video signal is read out of said memory from the period at which the video signal is stored, comprising: an enlarged scanning line preparation circuit for preparing, from said video signal, a first scanning line signal and a second scanning line, first and second buffer memories for holding said first scanning line signal during a period of one field, third and fourth buffer memories for holding said second scanning line signal during a period of one field, a first switch circuit for switching output signals of said first and second buffer memories field by field, a second switch circuit for switching output signals of said third and fourth buffer memories field by field, and a third switch circuit for switching output signals of said first and second switch circuits, whereby said video signal is delayed by one or more fields to permit enlarged display.
Claim 2
Dependent Claim
186 words
A video signal processing circuit capable of enlarging and displaying a picture and adapted to store an quantized video signal at a predetermined period in a memory and perform enlarged display of an original image by changing the period at which the video signal is read out of said memory from the period at which the video signal is stored, comprising: an enlarged scanning line preparation circuit for preparing, from said video signal, a first scanning line signal and a second scanning line, first and second buffer memories for holding said first scanning line signal during a period of one field, third and fourth buffer memories for holding said second scanning line signal during a period of one field, a first switch circuit for switching output signals of said first and second buffer memories field by field, a second switch circuit for switching output signals of said third and fourth buffer memories field by field, and a third switch circuit for switching output signals of said first and second switch circuits, whereby said video signal is delayed by one or more fields to permit enlarged display.
Claim 3
Dependent Claim
46 words
A video signal processing circuit capable of enlarging and displaying a picture according to claim 1 further comprising: a progressive scan conversion circuit coupled to input terminals or the output terminal of said third switch circuit, thereby permitting enlarged display of a picture under noninterlace scanning.
Claim 4
Dependent Claim
224 words
A video signal processing circuit capable of enlarging and displaying a picture and provided with a frame memory for at least one frame delaying an input video signal, a motion adaptive luminance and chrominance (Y/C) separation circuit using input and output signals of said frame memory, a field memory for one field delaying the output signal of said Y/C separation circuit, and a motion adaptive scanning line interpolation circuit using input and output signals of said field memory, said processing circuit comprising: a first delay circuit for delaying the output signal of said Y/C separation circuit, a first switch circuit for switching the output of said first delay circuit and the input video signal and applying a resulting signal to said frame memory, a second delay circuit for delaying the output signal of said scanning line interpolation circuit, a second switch circuit for switching the output of said second delay circuit and the output of said Y/C separation circuit and applying a resulting signal to said field memory, a third switch circuit for switching the output of said Y/C separation circuit and the output of said frame memory, a fourth switch circuit for switching the output of said scanning line interpolation circuit and the output of said field memory, and a fifth switch for switching the outputs of said third and fourth switch circuits.
Claim 5
Dependent Claim
224 words
A video signal processing circuit capable of enlarging and displaying a picture and provided with a frame memory for at least one frame delaying an input video signal, a motion adaptive luminance and chrominance (Y/C) separation circuit using input and output signals of said frame memory, a field memory for one field delaying the output signal of said Y/C separation circuit, and a motion adaptive scanning line interpolation circuit using input and output signals of said field memory, said processing circuit comprising: a first delay circuit for delaying the output signal of said Y/C separation circuit, a first switch circuit for switching the output of said first delay circuit and the input video signal and applying a resulting signal to said frame memory, a second delay circuit for delaying the output signal of said scanning line interpolation circuit, a second switch circuit for switching the output of said second delay circuit and the output of said Y/C separation circuit and applying a resulting signal to said field memory, a third switch circuit for switching the output of said Y/C separation circuit and the output of said frame memory, a fourth switch circuit for switching the output of said scanning line interpolation circuit and the output of said field memory, and a fifth switch for switching the outputs of said third and fourth switch circuits.
Claim 6
Dependent Claim
44 words
A video signal processing circuit capable of enlarging and displaying a picture according to claim 3 further comprising: a progressive scan conversion circuit coupled to the input terminal or the output terminal of said fifth switch circuit, thereby permitting enlarged display under noninterlace scanning
Claim 7
Dependent Claim
59 words
A video signal processing circuit capable of enlarging and displaying a picture according to claim 3 wherein said scanning line interpolation circuit comprises: a line interpolation circuit using a circuit for a delay of at least one horizontal scanning period and an addition circuit, and said one horizontal scanning period delay circuit also functions as said first delay circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-01 | 1994-12-31 | 1995-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-01 | 1998-12-31 | 1999-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-01 | 2002-12-31 | 2003-07-02 | $7700.00 | Window Closed / Lapsed |