Adaptive array processor

Claim 1

An off-line processor arrangement for a broadband accelerated convergence adaptive antenna array, the arrangement including a plurality of antenna elements, a like plurality of tapped delay lines, the signal output of each antenna element being applied to the input of a respective one of the tapped delay lines, a number of individual signal weighting means to each of which is applied the output of a respective one of the outputs of a tapped delay line, and a beamforming network to which is applied the outputs of the weighting means, the arrangement further including lattice filter means to which are applied the signal outputs of the antenna elements, means for applying to the lattice filter means the output response of the beamforming network, wherein the lattice filter means is arranged to compute sets of weight correction vectors for respective antenna element outputs, means for storing weight coefficients to be applied to the individual signal weighting means, means for applying said computed weight correction vectors to said storing means to update said stored weight coefficients, and means for applying said stored and updated weight coefficients at timed intervals to the individual signal weighting means, to weight the outputs of the tapped delay lines.