Fabrication of devices having laterally isolated semiconductor regions

Claim 2

A process for sealing and isolating semiconductor within a device structure comprising the steps of: providing a semiconductor substrate; forming a first insulating layer on said semiconductor substrate; forming a semiconductor layer on said first insulating layer; forming a first dielectric layer on said semiconductor layer; forming openings in said first dielectric layer, said openings extending to said semiconductor layer; forming sidewall spacers in said openings; partially oxidizing said semiconductor layer between said sidewall spacers; removing said sidewall spacers to expose unoxidized portions of said semiconductor layer in said openings; etching completely through said exposed, unoxidized portions of said semiconductor layer to form sidewall openings; and forming sidewalls in said sidewall openings, said sidewalls being impervious to impurities and oxidation.

Claim 3

The process of claim 1 further comprising the step of completely oxidizing the semiconductor layer remaining in the openings following the forming sidewalls step.

Claim 4

The process of claim 1 wherein the partially oxidized portions of the semiconductor layer in the openings are removed along with the first dielectric layer following the formation of the sidewall openings and a second dielectric layer is subsequently formed on the structure.

Claim 5

The process of claim 1 further comprising the step of forming a second insulating layer on said semiconductor regions, said second insulating layer being impervious to impurities and oxidation.

Claim 6

The process of claim 4 wherein the first insulating layer is impervious to impurities and oxidation.

Claim 7

The process of claim 5 further comprising the step of forming an isolating layer between the semiconductor substrate and the first insulating layer.

Claim 8

The process of claim 6 wherein the semiconductor substrate comprises silicon, the semiconductor regions comprise amorphous or polycrystalline silicon, the insulating sidewalls and layers comprise silicon nitride and the isolating layer comprises silicon dioxide.

Claim 9

A process for sealing and isolating semiconductor regions in a device structure comprising the steps of: providing a semiconductor substrate; forming a first insulating layer on said semiconductor substrate; forming a semiconductor layer on said first insulating layer; forming a second insulating layer on said semiconductor layer, said second insulating layer being comprised of a first dielectric material that is impervious to impurities and oxidation; forming a dielectric layer comprised of a second dielectric material on said second insulating layer; forming openings through said dielectric and second insulating layers, said openings extending to said semiconductor layer; forming sidewall spacers comprised of said first dielectric material in said openings; partially oxidizing said semiconductor layer between said sidewall spacers; removing said sidewall spacers from said openings to expose unoxidized portions of said semiconductor layer; etching completely through said exposed, unoxidized portions of said semiconductor layer to form sidewall openings; forming sidewalls in said sidewall openings, said sidewalls being comprised of said first dielectric material; completely oxidizing said semiconductor layer remaining in said openings; and etching said entire device structure back to said insulating layer.

Claim 10

A process for sealing and isolating semiconductor regions in a device structure comprising the steps of: providing a semiconductor substrate; forming a first insulating layer on said semiconductor substrate; forming a semiconductor layer on said first insulating layer; forming a second insulating layer on said semiconductor layer, said second insulating layer being comprised of a first dielectric material that is impervious to impurities and oxidation; forming a dielectric layer comprised of a second dielectric material on said second insulating layer; forming openings through said dielectric and second insulating layers, said openings extending to said semiconductor layer; forming sidewall spacers comprised of said first dielectric material in said openings; partially oxidizing said semiconductor layer between said sidewall spacers; removing said sidewall spacers from said openings to expose unoxidized portions of said semiconductor layer; etching completely through said exposed, unoxidized portions of said semiconductor layer to form sidewall openings; forming sidewalls in said sidewall openings, said sidewalls being comprised of said first dielectric material; completely oxidizing said semiconductor layer remaining in said openings; and etching said entire device structure back to said insulating layer.

Claim 11

The process of claim 8 further comprising the steps of: completely removing the second insulating layer; oxidizing the exposed surfaces of the semiconductor layer; and doping the various regions of said semiconductor layer.

Claim 12

The process of claim 8 wherein an isolating layer comprised of the second dielectric material is formed on the entire device structure.

Claim 13

The process of claim 8 wherein the first insulating layer comprises the first dielectric material.

Claim 14

The process of claim 11 wherein an isolation layer comprised of the second dielectric material is formed between the semiconductor substrate and the first insulating layer disposed beneath the semiconductor layer.

Claim 15

The process of claim 1 wherein the semiconductor substrate comprises silicon, the semiconductor layer comprises amorphous or polycrystalline silicon, the first dielectric material comprises silicon nitride and the second dielectric material comprises silicon dioxide.

Claim 16

A process for sealing and isolating semiconductor regions in a device structure comprising the steps of: providing a silicon substrate; forming a first silicon nitride insulating layer on said silicon substrate; forming a polysilicon layer on said first silicon nitride insulating layer; forming a second silicon nitride insulating layer on said polysilicon layer; forming a silicon dioxide layer on said second silicon nitride insulating layer; etching openings through said silicon dioxide layer and said second silicon nitride insulating layer, said openings extending to said polysilicon layer; forming a silicon nitride sidewall spacer layer on said silicon dioxide layer and in said openings; patterning and etching said silicon nitride sidewall spacer layer to form sidewall spacers in said openings; partially oxidizing said polysilicon layer in said openings between said sidewall spacers; removing said sidewall spacers to expose unoxidized portions of said polysilicon layer in said openings; etching completely through said exposed, unoxidized portions of said polysilicon layer in said openings to form sidewall openings; forming a silicon nitride conformal layer in said sidewall openings, in said openings and on said silicon dioxide layer; removing said silicon nitride conformal layer from said silicon dioxide layer and said oxidized polysilicon layer in said openings; completely oxidizing said polysilicon layer in said openings; and etching said entire device structure back to said second silicon nitride insulating layer.

Claim 17

A process for sealing and isolating semiconductor regions in a device structure comprising the steps of: providing a silicon substrate; forming a first silicon nitride insulating layer on said silicon substrate; forming a polysilicon layer on said first silicon nitride insulating layer; forming a second silicon nitride insulating layer on said polysilicon layer; forming a silicon dioxide layer on said second silicon nitride insulating layer; etching openings through said silicon dioxide layer and said second silicon nitride insulating layer, said openings extending to said polysilicon layer; forming a silicon nitride sidewall spacer layer on said silicon dioxide layer and in said openings; patterning and etching said silicon nitride sidewall spacer layer to form sidewall spacers in said openings; partially oxidizing said polysilicon layer in said openings between said sidewall spacers; removing said sidewall spacers to expose unoxidized portions of said polysilicon layer in said openings; etching completely through said exposed, unoxidized portions of said polysilicon layer in said openings to form sidewall openings; forming a silicon nitride conformal layer in said sidewall openings, in said openings and on said silicon dioxide layer; removing said silicon nitride conformal layer from said silicon dioxide layer and said oxidized polysilicon layer in said openings; completely oxidizing said polysilicon layer in said openings; and etching said entire device structure back to said second silicon nitride insulating layer.

Claim 18

The process of claim 14 further comprising the steps of: completely removing the second silicon nitride insulating layer; thermally oxidizing the exposed surfaces of the polysilicon layer; and doping the various regions of said polysilicon layer.

Claim 19

The process of claim 14 wherein a silicon dioxide isolating layer is formed on the entire device structure.

Claim 20

The process of claim 14 wherein a silicon dioxide isolating layer is formed between the silicon substrate and the first silicon nitride insulating layer.

Claim 21

A process for sealing and isolating semiconductor regions in a device structure comprising the steps of: providing a semiconductor substrate; forming a first insulating layer on said semiconductor substrate; forming a semiconductor layer on said first insulating layer; forming a second insulating layer on said semiconductor layer, said insulating layer being comprised of a first dielectric material that is impervious to impurities and oxidation; forming a dielectric layer comprised of a second dielectric material on said second insulating layer; forming openings through said dielectric and second insulating layers, said openings extending to said semiconductor layer; forming sidewall spacers comprised of said first dielectric material in said openings; partially oxidizing said semiconductor layer between said sidewall spacers; removing said sidewall spacers from said openings to expose unoxidized portions of said semiconductor layer; etching completely through said exposed unoxidized portions of said semiconductor layer to form sidewall openings; removing said partially oxidized portions of said semiconductor layer and said dielectric layer; and forming sidewalls in said sidewall openings, said sidewalls being comprised of said first dielectric material.

Claim 22

A process for sealing and isolating semiconductor regions in a device structure comprising the steps of: providing a semiconductor substrate; forming a first insulating layer on said semiconductor substrate; forming a semiconductor layer on said first insulating layer; forming a second insulating layer on said semiconductor layer, said insulating layer being comprised of a first dielectric material that is impervious to impurities and oxidation; forming a dielectric layer comprised of a second dielectric material on said second insulating layer; forming openings through said dielectric and second insulating layers, said openings extending to said semiconductor layer; forming sidewall spacers comprised of said first dielectric material in said openings; partially oxidizing said semiconductor layer between said sidewall spacers; removing said sidewall spacers from said openings to expose unoxidized portions of said semiconductor layer; etching completely through said exposed unoxidized portions of said semiconductor layer to form sidewall openings; removing said partially oxidized portions of said semiconductor layer and said dielectric layer; and forming sidewalls in said sidewall openings, said sidewalls being comprised of said first dielectric material.

Claim 23

The process of claim 18 further comprising the steps of: completely removing the second insulating layer; oxidizing the exposed surfaces of the semiconductor layer; and doping the various regions of said semiconductor layer.

Claim 24

The process of claim 18 wherein an isolating layer comprised of the second dielectric material is formed on the entire device structure.

Claim 25

The process of claim 18 wherein the first insulating layer comprised of the first dielectric material.

Claim 26

The process of claim 21 wherein an isolation layer comprised of the second dielectric material is formed between the semiconductor substrate and the first insulating layer disposed beneath the semiconductor layer.

Claim 27

The process of claim 21 wherein the semiconductor substrate comprises silicon, the semiconductor layer comprises amorphous or polycrystalline silicon, the first dielectric material comprises silicon nitride and the second dielectric material comprises silicon dioxide.

Claim 28

A process for sealing and isolating semiconductor regions in a device structure comprising the steps of: providing a silicon substrate; forming a first silicon nitride insulating layer on said silicon substrate; forming a polysilicon layer on said first silicon nitride insulating layer; forming a second silicon nitride insulating layer on said polysilicon layer, forming a silicon dioxide layer on said silicon nitride insulating layer; patterning and etching openings through said silicon dioxide layer and said second silicon nitride insulating layer, said openings extending to said polysilicon layer; forming a silicon nitride sidewall spacer layer on said silicon dioxide layer and in said openings; patterning and etching said silicon nitride sidewall spacer layer to form sidewall spacers in said openings; partially oxidizing said polysilicon layer in said openings btween said sidewall spacers; removing said sidewall spacers to expose unoxidized portions of said polysilicon layer in said openings; etching completely through said exposed, unoxidized portions of said polysilicon layer in said openings to form sidewall openings; removing said partially formed oxidized portions of said polysilicon layer and said silicon dioxide layer; and forming a silicon nitride conformal layer in said sidewall openings and on said second silicon nitride insulating layer.

Claim 29

A process for sealing and isolating semiconductor regions in a device structure comprising the steps of: providing a silicon substrate; forming a first silicon nitride insulating layer on said silicon substrate; forming a polysilicon layer on said first silicon nitride insulating layer; forming a second silicon nitride insulating layer on said polysilicon layer, forming a silicon dioxide layer on said silicon nitride insulating layer; patterning and etching openings through said silicon dioxide layer and said second silicon nitride insulating layer, said openings extending to said polysilicon layer; forming a silicon nitride sidewall spacer layer on said silicon dioxide layer and in said openings; patterning and etching said silicon nitride sidewall spacer layer to form sidewall spacers in said openings; partially oxidizing said polysilicon layer in said openings btween said sidewall spacers; removing said sidewall spacers to expose unoxidized portions of said polysilicon layer in said openings; etching completely through said exposed, unoxidized portions of said polysilicon layer in said openings to form sidewall openings; removing said partially formed oxidized portions of said polysilicon layer and said silicon dioxide layer; and forming a silicon nitride conformal layer in said sidewall openings and on said second silicon nitride insulating layer.

Claim 30

The process of claim 24 further comprising the steps of: completely removing the second silicon nitride insulating layer and conformal layer from the top of the polysilicon layer; thermally oxidizing the exposed surfaces of said polysilicon layer; and doping the various regions of said polysilicon layer.

Claim 31

The process of claim 24 wherein a silicon dioxide isolating layer is formed on the entire device structure.

Claim 32

The process of claim 24 wherein a silicon dioxide isolating layer is formed between the silicon substrate and the first silicon nitride insulating layer.