Microprocessor with option area adjacent CPU core facilitating interfacing with peripheral devices

Claim 2

A microprocessor having architecture comprising: a CPU core having a first, second and third peripheral edges, which first and second peripheral edges are located on opposite sides of said CPU core and connected by said third peripheral edge; a RAM adjoining said first peripheral edge of said CPU core; a ROM adjoining said second peripheral edge of said CPU core; and an input/output option structurally adapted for interfacing with various peripheral devices and adjoining said third peripheral edge of said CPU core and parallel peripheral edges of said RAM and ROM.

Claim 3

The microprocessor architecture as set forth in claim 1, wherein said CPU core, comprises an instruction decoder adjoining said second peripheral edge.

Claim 4

The microprocessor architecture as set forth in claim 2, wherein said CPU core further comprises various function blocks respectively lying perpendicular to said first and second peripheral edges and arranged side-by-side and parallel to each other.

Claim 5

The microprocessor architecture as set forth in claim 3, wherein said function blocks lie about parallel to said input/output option.

Claim 6

The microprocessor architecture as set forth in claim 4, wherein said function blocks include a timer register.

Claim 7

The microprocessor architecture as set forth in claim 4, wherein said function blocks include a serial input/output register.

Claim 8

The microprocessor architecture as set forth in claim 4, wherein said function blocks all have the same bit length and essentially the same number of bytes.

Claim 9

The microprocessor architecture as set forth in claim 1, which further comprises a plurality of peripheral input/output units interfacing with said input/output option, and said RAM has an address bus which also addresses said peripheral input/output units.

Claim 10

The microprocessor architecture as set forth in claim 7, wherein said CPU core has a RAM address decoder for locating addresses in said peripheral input/output units, which RAM address decoder has address decoding lines extending into said input/output option.

Claim 11

A microprocessor having architecture which is structurally adapted for embodiment on a single chip and for conveniently interfacing with various peripheral devices through an I/O option comprising: a CPU core structurally arranged on said substrate and comprising elements defining first, second, and third peripheral edges, said first and said second peripheral edges being located on opposite sides of said CPU core, said third peripheral edge connecting said first and said second peripheral edges; a RAM structurally positioned on said substrate adjacent said first peripheral edge of said CPU core; a ROM structurally positioned on said substrate and adjoining said second peripheral edge of said CPU core, opposite said first peripheral edge and said RAM; and, said I/O option for interfacing various peripheral devices located on said substrate adjoining said third peripheral edge of said CPU core and peripheral edges of both said RAM and said ROM.

Claim 12

A microprocessor having architecture which is structurally adapted for embodiment on a single chip and for conveniently interfacing with various peripheral devices through an I/O option comprising: a CPU core structurally arranged on said substrate and comprising elements defining first, second, and third peripheral edges, said first and said second peripheral edges being located on opposite sides of said CPU core, said third peripheral edge connecting said first and said second peripheral edges; a RAM structurally positioned on said substrate adjacent said first peripheral edge of said CPU core; a ROM structurally positioned on said substrate and adjoining said second peripheral edge of said CPU core, opposite said first peripheral edge and said RAM; and, said I/O option for interfacing various peripheral devices located on said substrate adjoining said third peripheral edge of said CPU core and peripheral edges of both said RAM and said ROM.

Claim 13

The microprocessor architecture as set forth in claim 10, wherein said CPU core comprises an instruction decoder adjoining said second peripheral edge.

Claim 14

The microprocessor architecture as set forth in claim 10, wherein said CPU core further comprises various function blocks respectively lying perpendicular to said first and second peripheral edges and arranged side-by-side and parallel to each other.

Claim 15

The microprocessor architecture as set forth in claim 10, wherein said function blocks lie about parallel to said input/output option.

Claim 16

The microprocessor architecture as set forth in claim 10, wherein said function blocks include a timer register.

Claim 17

The microprocessor architecture as set forth in claim 10, wherein said function blocks include a serial input/output register.

Claim 18

The microprocessor architecture as set forth in claim 10, wherein said function blocks all have the same bit length and essentially the same number of bytes.

Claim 19

The microprocessor architecture as set forth in claim 10, wherein further comprises a plurality of peripheral input/output units interfacing with said input/output option, and said RAM has an address bus which also addresses said peripheral input/output units.

Claim 20

The microprocessor architecture as set forth in claim 10, wherein said CPU core has a RAM address decoder for locating addresses in said peripheral input/output units, which RAM address decoder has address decoding lines extending into said input/output option.