High-gain low-noise amplifier

Claim 2

A high-gain, low-noise multiple stage solid-state amplifier, comprising: phase-inverting input stage means including a first FET for receiving a time-varying input signal and an output FET configured as a source follower, wherein a source terminal of the output FET presents a relatively low output impedance and provides a first output signal representing a substantially phase-inverted version of the input signal having a magnitude amplified by an input stage gain value; and phase non-inverting output stage means receiving the first output signal for providing a second output signal representing a substantially phase-inverted version of the input signal having a magnitude amplified by the product of an output stage voltage gain and the input stage voltage gain, the output stage including a second FET connected in a common gate configuration having a source terminal for receiving the first output signal and an output terminal, the source terminal receiving the first output signal and the output terminal providing a non-inverted amplified version of the first output signal; whereby the phase-inverting input stage means and phase non-inverting output stage means cooperate to provide the amplifier with high overall gain and wide bandwidth properties.

Claim 3

The amplifier of claim 1, in which the input stage includes an input terminal and the amplifier further comprising a feedback impedance electrically connected between the input terminal and the output terminal, thereby to form an amplifier of the transimpedance type.

Claim 4

The amplifier of claim 2, in which the feedback impedance includes a resistor.

Claim 5

The amplifier of claim 1, in which the first, second, and output FETs are of the gallium arsenide type.

Claim 6

The amplifier of claim 1, in which the first, second, and output FETs are implemented in integrated circuit form.

Claim 7

A high gain, low noise multiple stage solid-state amplifier, comprising: phase-inverting input stage means receiving a time-varying input signal for providing a first output signal representing a substantially phase-inverted version of the input signal having a magnitude amplified by an input stage gain value, the input stage means including a first transistor through which a transistor current flows and having a transistor current-dependent transconductance, the first transistor operatively connected to a load impedance to provide an input stage voltage gain that approximately equals the transconductance of the first transistor times the load impedance, and the input stage means further including supplemental bias current means for providing supplemental bias current that forms a component of the transistor current, the supplemental bias current affecting the transconductance of the first transistor and enabling a change in the input stage voltage gain with substantial mutual independence of the transconductance of the first transistor and the load impedance; and phase non-inverting output stage means receiving the first output signal for providing a second output signal representing a substantially phase-inverted version of the input signal having a magnitude amplified by the product of an output stage voltage gain and the input stage voltage gain, the output stage including a second transistor having an input terminal and an output terminal, the input terminal receiving the first output signal and the output terminal providing an non-inverted amplified version of the first output signal; whereby the phase-inverting output stage means and phase non-inverting output stage means cooperate to provide the amplifier with high overall gain and wide bandwidth properties.

Claim 8

A high gain, low noise multiple stage solid-state amplifier, comprising: phase-inverting input stage means receiving a time-varying input signal for providing a first output signal representing a substantially phase-inverted version of the input signal having a magnitude amplified by an input stage gain value, the input stage means including a first transistor through which a transistor current flows and having a transistor current-dependent transconductance, the first transistor operatively connected to a load impedance to provide an input stage voltage gain that approximately equals the transconductance of the first transistor times the load impedance, and the input stage means further including supplemental bias current means for providing supplemental bias current that forms a component of the transistor current, the supplemental bias current affecting the transconductance of the first transistor and enabling a change in the input stage voltage gain with substantial mutual independence of the transconductance of the first transistor and the load impedance; and phase non-inverting output stage means receiving the first output signal for providing a second output signal representing a substantially phase-inverted version of the input signal having a magnitude amplified by the product of an output stage voltage gain and the input stage voltage gain, the output stage including a second transistor having an input terminal and an output terminal, the input terminal receiving the first output signal and the output terminal providing an non-inverted amplified version of the first output signal; whereby the phase-inverting output stage means and phase non-inverting output stage means cooperate to provide the amplifier with high overall gain and wide bandwidth properties.

Claim 9

The amplifier of claim 6 in which the first and second transistors are of the field effect type and the second transistor is connected in a common gate configuration with its source constituting the input terminal and its drain constituting the output terminal.

Claim 10

The amplifier of claim 6 in which the input stage means includes an amplifier input terminal and the output stage means includes an amplifier output terminal, and further comprises a feedback impedance electrically connected between the amplifier input and output terminals to form a transimpedance amplifier.

Claim 11

The amplifier of claim 6 in which the output stage means further comprises an output transistor electrically connected to the output terminal of the second transistor to form an output buffer circuit, the second and output transistors cooperating to determine the output stage gain value.

Claim 12

The amplifier of claim 9, further comprising gain boost means cooperating with the second and output transistors to determine the output stage gain value.

Claim 13

The amplifier of claim 9, in which the input stage includes a third transistor configured in cascode arrangement with the first transistor, the first and third transistors are of the field effect type, and the third transistor has a drain terminal that provides a load current flowing through the load impedance, and further comprising current summing means for summing the load current and the supplemental bias current to produce the transistor current, the current summing means having an impedance value and the third transistor having an impedance at its drain terminal, and further comprising negative feedback means for lowering the impedance value of the current summing means and raising the impedance at the drain terminal of the third transistor.

Claim 14

The amplifier of claim 11, in which the negative feedback means includes a fourth transistor electrically connected to the current summing means and to the third transistor.

Claim 15

The amplifier of claim 6, in which a load current flows through the load impedance and further comprising current summing means for summing the load current and the supplemental bias current to produce the transistor current, and in which the input stage means further includes the first transistor, a third transistor having an output terminal and connected in cascode arrangement with the first transistor, and negative feedback means for lowering the impedance value of the current summing means and increasing the impedance at the output terminal of the third transistor.

Claim 16

The amplifier of claim 13, in which the negative feedback means comprises a fourth transistor electrically connected to the current summing means and to the third transistor, the fourth transistor providing negative feedback for raising the impedance at the output terminal of the third transistor to facilitate adjustment of the load impedance without changing the transconductance value of the first transistor.

Claim 17

The amplifier of claim 13, in which the third transistor is of the field effect type, and the output impedance of the third transistor appears at its drain terminal.

Claim 18

The amplifier of claim 6, further comprising negative feedback means electrically connected to the first transistor for providing the input stage means with an output impedance of relatively high value and thereby permitting the use of a load impedance of relatively high value to increase the voltage gain.

Claim 19

The amplifier of claim 6, in which the input stage means, the load impedance, and the supplemental bias current means are implemented in integrated circuit form.

Claim 20

The amplifier of claim 6, in which the first and second transistors are of the gallium arsenide type.

Claim 21

The amplifier of claim 6, in which the load impedance comprises a resistor.