Decoder error prevention apparatus for use in flash analog-to-digital converters

Claim 1

In a flash analog-to-digital converter of the type employing 2 n -1 comparators where n is a positive integer greater than 1 and selected according to the number of bits converted, each of said comparators having one input coupled to an associated tap on a reference biased resistance ladder and having another input coupled to an analog signal source with said comparators arranged from a lowest decision ordered comparator to a highest decision ordered comparator, where said comparator trip points are spaced one least significant bit apart so that a first plurality of comparators for a given input signal voltage exhibit a high output, while a second plurality exhibits a low output for the same given input voltage, whereby one of said comparators in said plurality has a high output with a lower least significant bit adjacent comparator having a low output and a higher least significant bit adjacent comparator having a high output so that said one comparator output is the desired selected output of said converter, whereby if said analog signal source is slewing rapidly more than one comparator in said plurality will undesirably provide an output due to adjacent comparators exhibiting high and low outputs, the combination therewith of apparatus for preventing such multiple outputs in a flash-type converter, comprising: means coupled to selected comparator outputs for detecting all the comparator output states for a given input signal voltage to determine the comparators providing said high output and the comparators providing said low output; and means coupled to said comparators for inhibiting any output from a comparator of a higher decision order when a lower decision order comparator is also providing said output, whereby only one lower order comparator will provide an output for said given input signal voltage.

Claim 9

A method for error prevention in a flash type analog-to-digital converter of the type employing a plurality of comparators with said comparators arranged from a lowest decision ordered comparator to a highest decision ordered comparator, each having one input coupled to an associated tap on a resistance reference ladder and each having another input adapted to be coupled to an analog input signal source for providing an output indicative of the value of said signal by determining the comparator output tap where all comparisons above and adjacent to said tap are high and all comparisons below and adjacent to said tap are low such that said determined output is high to thereby provide said output by testing for a high, high-low (HHL) sequence whereby if said input signal is slewing rapidly more than one HHL sequence will be undesirably provided, comprising the steps of: detecting all HHL sequences, inhibiting any higher order detected sequences with a detected lower order sequence to thereby prevent more than one sequence from being provided and using said detected lower sequence for determining said desired comparator output.

Claim 10

A method for error prevention in a flash type analog-to-digital converter of the type employing a plurality of comparators with said comparators arranged from a lowest decision ordered comparator to a highest decision ordered comparator, each having one input coupled to an associated tap on a resistance reference ladder and each having another input adapted to be coupled to an analog input signal source for providing an output indicative of the value of said signal by determining the comparator output tap where all comparisons above and adjacent to said tap are high and all comparisons below and adjacent to said tap are low such that said determined output is high to thereby provide said output by testing for a high, high-low (HHL) sequence whereby if said input signal is slewing rapidly more than one HHL sequence will be undesirably provided, comprising the steps of: detecting all HHL sequences, inhibiting any higher order detected sequences with a detected lower order sequence to thereby prevent more than one sequence from being provided and using said detected lower sequence for determining said desired comparator output.