Illegal sequence detection and protection circuit

Claim 2

A interface circuit for converting an input data sequence to an output data sequence, said input and output data sequences comprising the same number of bits, said output data sequence differing from said input data sequence if said input data sequence matches an illegal sequence comprising a predetermined sequence of N data bits, said interface circuit comprising: means for receiving said data sequence; means for storing at least one of the last N data bits received by said receiving means; means for determining if the previously received N data bits match said illegal sequence; means responsive to said determining means for altering one of the said data bits stored in said storing means if said data determining means determines that said previously received N data bits match said illegal sequence; and means for outputting the data bits stored in said storing means to form said output data sequence.

Claim 3

A interface circuit for converting an input data sequence to an output data sequence, said input and output data sequences comprising the same number of bits, said output data sequence differing from said input data sequence if said input data sequence matches an illegal sequence comprising a predetermined sequence of N data bits, said interface circuit comprising: means for receiving said data sequence; means for storing at least one of the last N data bits received by said receiving means; means for determining if the previously received N data bits match said illegal sequence; means responsive to said determining means for altering one of the said data bits stored in said storing means if said data determining means determines that said previously received N data bits match said illegal sequence; and means for outputting the data bits stored in said storing means to form said output data sequence, wherein said determining means generates an output signal having a logical value of "1" if said previously received N data bits match said illegal sequence and "0" otherwise, and wherein said storing means comprises a one bit adder for calculating the sum modulo 2 of first and second inputs, said first input being the last data bit received by said receiving means and said second input being said output signal, the output of said adder being said output data sequence.

Claim 4

A interface circuit for converting an input data sequence to an output data sequence, said input and output data sequences comprising the same number of bits, said output data sequence differing from said input data sequence if said input data sequence matches an illegal sequence comprising a predetermined sequence of N data bits, said interface circuit comprising: means for receiving said data sequence; means for storing at least one of the last N data bits received by said receiving means; means for determining if the previously received N data bits match said illegal sequence; means responsive to said determining means for altering one of the said data bits stored in said storing means if said data determining means determines that said previously received N data bits match said illegal sequence; and means for outputting the data bits stored in said storing means to form said output data sequence, wherein said determining means generates an output signal having a logical value of "1" if said previously received N data bits match said illegal sequence and "0" otherwise, and wherein said storing means comprises a one bit adder for calculating the sum modulo 2 of first and second inputs, said first input being the last data bit received by said receiving means and said second input being said output signal, the output of said adder being said output data sequence.

Claim 5

The interface circuit of claim 1 wherein said determining means further comprises means for generating an alarm signal in response to said output signal having a logical value of 1.

Claim 6

A interface circuit for converting an input data sequence to an output data sequence, said input and output data sequences comprising the same number of bits, said output data sequence differing from said input data sequence if said input data sequence matches an illegal sequence comprising a predetermined sequence of N data bits, said interface circuit comprising: means for receiving said data sequence; means for storing at least one of the last N data bits received by said receiving means; means for determining if the previously received N data bits match said illegal sequence; means responsive to said determining means for altering one of the said data bits stored in said storing means if said data determining means determines that said previously received N data bits match said illegal sequence; and means for outputting the data bits stored in said storing means to form said output data sequence, wherein said illegal sequence satisfies a recursive relation of the form s.sub.n =F(s.sub.n-1, s.sub.n-2, . . . , s.sub.n-k) wherein S n is the nth bit of said illegal sequence, k is a predetermined integer, and F is a predetermined function, and wherein said determining means comprises: a shift register including k stages; means for shifting each data bit received by said receiving means into the first stage of said shift register upon receipt of said data bit; means for computing a predetermined mathematical function of the data bits stored in said shift register to produce a numerical result after each data bit is received by said receiving means; means for counting the number of successive data bits received for which said numerical result did not change; and means for generating said output signal if said number exceeds a predetermined number.

Claim 7

A interface circuit for converting an input data sequence to an output data sequence, said input and output data sequences comprising the same number of bits, said output data sequence differing from said input data sequence if said input data sequence matches an illegal sequence comprising a predetermined sequence of N data bits, said interface circuit comprising: means for receiving said data sequence; means for storing at least one of the last N data bits received by said receiving means; means for determining if the previously received N data bits match said illegal sequence; means responsive to said determining means for altering one of the said data bits stored in said storing means if said data determining means determines that said previously received N data bits match said illegal sequence; and means for outputting the data bits stored in said storing means to form said output data sequence, wherein said illegal sequence satisfies a recursive relation of the form s.sub.n =F(s.sub.n-1, s.sub.n-2, . . . , s.sub.n-k) wherein S n is the nth bit of said illegal sequence, k is a predetermined integer, and F is a predetermined function, and wherein said determining means comprises: a shift register including k stages; means for shifting each data bit received by said receiving means into the first stage of said shift register upon receipt of said data bit; means for computing a predetermined mathematical function of the data bits stored in said shift register to produce a numerical result after each data bit is received by said receiving means; means for counting the number of successive data bits received for which said numerical result did not change; and means for generating said output signal if said number exceeds a predetermined number.

Claim 8

The interface circuit of claim 4 wherein k is equal to 7 and wherein s.sub.n =s.sub.n-6 +s.sub.n-7.

Claim 9

A circuit for determining if an input data sequence includes a sub-sequence of an illegal sequence satisfying a recursive relation of the form s.sub.n =F(s.sub.n-1, s.sub.n-2, . . . , s.sub.n-k) wherein S n is the nth bit of said data sequence, k is a predetermined integer, and F is a predetermined function, circuit comprising: means for receiving said input data sequence; a shift register including k stages; means for shifting each data bit received by said receiving means into the first stage of said shift register upon receipt of said data bit; means for computing a predetermined mathematical function of the data bits stored in said shift register to produce a numerical result dependent upon said function F after each bit of said input data sequence is received by said receiving means; means for counting the number of successive input data bits received for which said numerical result did not change; and means for generating said output signal if said number exceeds a predetermined number.

Claim 10

A circuit for determining if an input data sequence includes a sub-sequence of an illegal sequence satisfying a recursive relation of the form s.sub.n =F(s.sub.n-1, s.sub.n-2, . . . , s.sub.n-k) wherein S n is the nth bit of said data sequence, k is a predetermined integer, and F is a predetermined function, circuit comprising: means for receiving said input data sequence; a shift register including k stages; means for shifting each data bit received by said receiving means into the first stage of said shift register upon receipt of said data bit; means for computing a predetermined mathematical function of the data bits stored in said shift register to produce a numerical result dependent upon said function F after each bit of said input data sequence is received by said receiving means; means for counting the number of successive input data bits received for which said numerical result did not change; and means for generating said output signal if said number exceeds a predetermined number.