US5021872A
Expired / Lapsed
US
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Phase locked subcarrier regenerator
Assignee: RCA Licensing Corp
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Filing: 1990-02-14
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Granted: 1991-06-04
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Expires: 2010-02-14
Abstract
Abstract Apparatus for generating a signal having a predetermined frequency relationship with a subcarrier includes a counter for counting cycles of said subcarrier. Count values from the counter are coupled as address values to a memory circuit. The memory circuit is preprogrammed to provide a signal having the desired frequency responsive to successive address values applied by the counter.
Inventors
- 👤 Shinichi Shiratsuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:30
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/79; H04N9/87; H04N9/89; H04N9/896; H04N9/44; H04N9/45; H04N7/00; H04N7/08
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
129 words
A phase locked frequency signal generator, comprising: a source of a clock signal; an initialization pulse generating means coupled to receive a color subcarrier signal which is phase locked to a color burst and a horizontal synchronization signal, and responsive to said clock signal for generating an initialization pulse; means coupled to receive said initialization pulse and responsive to said clock signal for generating a memory read address signal; and memory means programmed at respective memory locations with a series of sampled data representing a frequency signal to be generated, the frequency of said frequency signal having a predetermined relationship with the frequency of said clock signal, said memory means being coupled to receive said memory read address signal for generating the frequency signal consisting of said sampled data.
Claim 2
Dependent Claim
129 words
A phase locked frequency signal generator, comprising: a source of a clock signal; an initialization pulse generating means coupled to receive a color subcarrier signal which is phase locked to a color burst and a horizontal synchronization signal, and responsive to said clock signal for generating an initialization pulse; means coupled to receive said initialization pulse and responsive to said clock signal for generating a memory read address signal; and memory means programmed at respective memory locations with a series of sampled data representing a frequency signal to be generated, the frequency of said frequency signal having a predetermined relationship with the frequency of said clock signal, said memory means being coupled to receive said memory read address signal for generating the frequency signal consisting of said sampled data.
Claim 3
Dependent Claim
88 words
The phase locked frequency generator set forth in claim 1 wherein said means for generating said memory read address signal comprises: a counter having at least one reset input terminal, a clock input terminal, and having an output terminal for providing count values corresponding to said read address signal; a decoder coupled to said output terminal for detecting a predetermined count value and generating a reset signal responsive thereto; and means for coupling said initialization pulse and said reset pulse to said at least one reset input terminal.
Claim 4
Dependent Claim
62 words
The phase locked frequency generator set forth in claim 1 wherein said initialization pulse generating means includes; means including counting means, responsive to said clock signal, for generating a pulse signal at predetermined intervals; and means responsive to said pulse signal and said color subcarrier signal for providing said initialization pulse in accordance with a predetermined phase of said color subcarrier signal.
Claim 5
Dependent Claim
127 words
A phase locked frequency signal generator for generating a signal of frequency fc phase locked to a signal of frequency fsc, where fc is equal to n/m times fsc, and n and m are integers, said generator comprising: a terminal for receiving a clock signal of frequency k times fsc, where k is an integer; a counter, responsive to said clock signal, for sequentially counting modulo k times m, to repeatedly generate a series of memory read address values; and memory means, programmed with data at respective address locations corresponding to amplitude values of said signal of frequency fc, and responsive to said memory read address values, for providing at an output thereof a sequence of data representing a binary representation of said signal of frequency fc.
Claim 6
Dependent Claim
127 words
A phase locked frequency signal generator for generating a signal of frequency fc phase locked to a signal of frequency fsc, where fc is equal to n/m times fsc, and n and m are integers, said generator comprising: a terminal for receiving a clock signal of frequency k times fsc, where k is an integer; a counter, responsive to said clock signal, for sequentially counting modulo k times m, to repeatedly generate a series of memory read address values; and memory means, programmed with data at respective address locations corresponding to amplitude values of said signal of frequency fc, and responsive to said memory read address values, for providing at an output thereof a sequence of data representing a binary representation of said signal of frequency fc.
Claim 7
Dependent Claim
84 words
The phase locked frequency generator set forth in claim 4 wherein said counter for generating said memory read address values comprises: a counter having at least one reset input terminal, a clock input terminal, and having an output terminal for providing count values corresponding to said read address values; a decoder coupled to said output terminal for detecting a predetermined count value and generating a reset signal responsive thereto; and means for coupling said reset signal to said at least one reset input terminal.
Claim 8
Dependent Claim
64 words
The phase locked frequency generator set forth in claim 5 further including: an initialization pulse generating means coupled to receive a signal of frequency fc, which is phase locked to a color burst, and a horizontal synchronization signal, and responsive to said clock signal for generating an initialization pulse; and means for coupling said initialization pulse to said at least one reset input terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-03 | 1994-12-03 | 1995-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-03 | 1998-12-03 | 1999-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-03 | 2002-12-03 | 2003-06-04 | $7700.00 | Window Closed / Lapsed |