Demodulation method and demodulator for digital signals with amplitudes of constant envelope, continuously modulated in phase and/or in frequency

Claim 3

A method according to claim 1, wherein the encoding cost has a maximum value when the computed differential phase angle corresponds to the instants of synchronization and a null value in the middle of the interval between the consecutive instants of synchronization.

Claim 4

A method according to claim 2, wherein the law of variation of the encoding cost is linear.

Claim 5

A method according to claim 2, wherein the law of the encoding cost is nonlinear.

Claim 6

A demodulator of digital signals, continuously modulated in phase and/or frequency, the digital signals consisting of sequences of symbols that have the same duration T and are juxtaposed with one another in time, the symbols being transmitted by means of phase and/or frequency jumps, comprising: a shaping circuit to detect the phase of the signal modulated in the form of a signal of an amplitude variable as a function of the variations in phase of the modulating signal, and to sample the signal of variable amplitude obtained according to the sampling period T/N, a unit for the computation of the differential phase angle dφ between each phase angle of a detected current symbol of the homologue sample located at the same place in the symbol detected at the previous symbol time, a memorizing unit to memorize, for a duration of L symbols, each differential phase sample dφ; an encoding device to encode each differential phase angle give by the computation unit, and the differential phase angle of a same order memorized in the memorization unit computed L symbols earlier, in assigning them as encoding cost that depends on their amplitude, an adder/accumulator circuit to mutually substrate the costs that are computed by the encoding device and separated in the time of the duration of L symbols, and to add to the result of the subtraction during the period of L symbols; the encoding costs obtained for the samples of the same order inside each sample, a comparison circuit to identify, among the same obtained, that sum which gives the greatest result, a buffer register to memorize the the place number occupied in each symbol by the sample that has contributed to obtaining the sum giving the greatest results, a control logic to select the synchronization clock has the which matches with the place number of the memorized sample and a decoder to decode the differential phase angle corresponding to the place number of the sample memorized in the buffer register.

Claim 7

A demodulator of digital signals, continuously modulated in phase and/or frequency, the digital signals consisting of sequences of symbols that have the same duration T and are juxtaposed with one another in time, the symbols being transmitted by means of phase and/or frequency jumps, comprising: a shaping circuit to detect the phase of the signal modulated in the form of a signal of an amplitude variable as a function of the variations in phase of the modulating signal, and to sample the signal of variable amplitude obtained according to the sampling period T/N, a unit for the computation of the differential phase angle dφ between each phase angle of a detected current symbol of the homologue sample located at the same place in the symbol detected at the previous symbol time, a memorizing unit to memorize, for a duration of L symbols, each differential phase sample dφ; an encoding device to encode each differential phase angle give by the computation unit, and the differential phase angle of a same order memorized in the memorization unit computed L symbols earlier, in assigning them as encoding cost that depends on their amplitude, an adder/accumulator circuit to mutually substrate the costs that are computed by the encoding device and separated in the time of the duration of L symbols, and to add to the result of the subtraction during the period of L symbols; the encoding costs obtained for the samples of the same order inside each sample, a comparison circuit to identify, among the same obtained, that sum which gives the greatest result, a buffer register to memorize the the place number occupied in each symbol by the sample that has contributed to obtaining the sum giving the greatest results, a control logic to select the synchronization clock has the which matches with the place number of the memorized sample and a decoder to decode the differential phase angle corresponding to the place number of the sample memorized in the buffer register.

Claim 8

A demodulator according to claim 6, wherein the encoding circuit comprises a programmable read-only memory to memorize, in the form of tables, the different costs to be assigned to each differential phase computed by the computation unit.

Claim 9

A demodulator according to claim 6, further comprising a deviation counter controlled by the symbol frequency to estimate the deviation of the digital signal to address the cost tables as a function of the estimated deviation.

Claim 10

A demodulator according to claim 6, wherein the deviation counter transmits the value of the estimated deviation to the decoder through the buffer register and the control logic to perform a translation equal to the value of the deviation of the differential phase of the symbols to be decoded.

Claim 11

A demodulator according to claim 8, wherein the adder/accumulator circuit is controlled by the deviation counter.