Dynamic semiconductor memory device having improved voltage read-out

Claim 2

A semiconductor memory device comprising: a bit line pair composed of a first portion and a second portion; a plurality of memory cells connected to each bit line of the bit line pair of said first portion; first potential generating means connected to each of the bit lines of the bit line pair of said second portion for generating a first potential in response to potential of each of the bit lines of the bit line pair of said second portion and for supplying a first bit line of the bit line pair of said second portion with said first potential; second potential generating means connected to each of the bit lines of the bit line pair of said first portion for generating a second potential less than the first potential in response to potential of each of the bit lines of the bit line pair of said first portion and for supplying a second bit line of the bit line pair of said first portion with said second potential; and potential control means connected in series on each of the bit lines of the bit line pair between said first portion and said second portion of said bit line pair for dropping and transmitting the said first potential supplied to said first bit line of the bit line pair of said second portion onto said first bit line of the bit line pair of said first portion, said dropped and transmitted potential being larger than said second potential.

Claim 3

A semiconductor memory device as set forth in claim 1, wherein said first potential generating means is a P-type sense amplifier, said second potential generating means is an N-type sense amplifier, said potential control means is an N-channel MOS transistor having a threshold voltage, and said first potential is attenuated to a third potential equal in value to a difference between said threshold voltage and said first potential.

Claim 4

A semiconductor memory device as set forth in claim 2, wherein each of said memory cells holds one of said second potential and said third potential.

Claim 5

A semiconductor memory device comprising: at least a pair of bit lines; at least two memory cells connected to said bit lines for holding one of a first potential and a second potential having a value less than said first potential; selective means for selecting any of said memory cells; and reading-out means for reading out one of said first potential and said second potential held in a selected memory cell onto a bit line connected to the selected memory cell in response to an output of said selective means; wherein potential of said bit line is varied based on a potential read out by the reading-out means, said memory device further comprising: second potential generating means connected to each of the bit lines for generating said second potential in response to variation of the potential of the connected bit line; third potential generating means connected to each of the bit lines for generating a third potential larger than said first potential in response to variation of the potential of the connected bit line; potential control means connected between said third potential generating means and each of the bit lines for supplying one of the bit lines with said third potential by said third potential generating means as fourth potential less than said third potential and larger than said first potential; connecting means connected between said second potential generating means and each of the bit lines for supplying other of the bit lines with said second potential by said second potential generating means; and equalizing means for equalizing potential of each of the bit lines generated by said potential control means and said connecting means into an intermediate potential between said third and said second potentials, wherein said selective means is activated so that each of the bit lines is held to the intermediate potential by said equalizing means.

Claim 6

A semiconductor memory device comprising: at least a pair of bit lines; at least two memory cells connected to said bit lines for holding one of a first potential and a second potential having a value less than said first potential; selective means for selecting any of said memory cells; and reading-out means for reading out one of said first potential and said second potential held in a selected memory cell onto a bit line connected to the selected memory cell in response to an output of said selective means; wherein potential of said bit line is varied based on a potential read out by the reading-out means, said memory device further comprising: second potential generating means connected to each of the bit lines for generating said second potential in response to variation of the potential of the connected bit line; third potential generating means connected to each of the bit lines for generating a third potential larger than said first potential in response to variation of the potential of the connected bit line; potential control means connected between said third potential generating means and each of the bit lines for supplying one of the bit lines with said third potential by said third potential generating means as fourth potential less than said third potential and larger than said first potential; connecting means connected between said second potential generating means and each of the bit lines for supplying other of the bit lines with said second potential by said second potential generating means; and equalizing means for equalizing potential of each of the bit lines generated by said potential control means and said connecting means into an intermediate potential between said third and said second potentials, wherein said selective means is activated so that each of the bit lines is held to the intermediate potential by said equalizing means.

Claim 7

A semiconductor memory device as set forth in claim 4, wherein said reading-out means includes a first N-channel MOS transistor, having a first threshold voltage, wherein a sum of said threshold voltage of said first transistor and said first potential is equal to said third potential.

Claim 8

A semiconductor memory device as set forth in claim 5, wherein said potential control means includes a second N-channel MOS transistor, having a threshold voltage, wherein the difference between said threshold voltage of said second transistor and said third potential is equal to said fourth potential.

Claim 9

A semiconductor memory device as set forth in claim 6, wherein the threshold voltage of said first transistor is equal to the threshold voltage of said second transistor.

Claim 10

A semiconductor memory device as set forth in claim 4, wherein said third potential generating means generates said third potential in response to a rise in potential on the bit lines caused by the presence of the first potential read out by the reading-out means.

Claim 11

A semiconductor memory device as set forth in claim 8, wherein said second potential generating means generates said second potential in response to a drop in potential on the bit lines caused by the presence of the second potential read out by said reading-out means.

Claim 12

A semiconductor memory device as set forth in claim 4, wherein said third potential generating means is a sense amplifier including a plurality of P-channel MOS transistors.

Claim 13

A semiconductor memory device as set forth in claim 4, wherein the second potential generating means is a sense amplifier including a plurality of N-channel MOS transistors.

Claim 14

A semiconductor memory device comprising: a plurality of memory cells each comprising N-channel MOS first transistor and a capacitor, said capacitor holding one of first potential and ground potential, said memory cells being arranged in plural rows and plural columns; a plurality of word lines installed corresponding to each row of the memory cells and used to select the memory cells of each row; a plurality of bit line pairs installed corresponding to every of said bit line pairs of the memory cells, the bit lines included in each column being connected to a first transistor each of the corresponding memory cells; a plurality of first sense amplifiers connected to each of said bit line pairs for generating a potential equal to a power source potential; a plurality of second sense amplifiers connected to each of said bit line pairs for amplifying the potential of one of the bit lines included in the connected bit line pair into the ground potential; a plurality of N-channel MOS second transistors each connected between each of said first sense amplifiers and each of the bit lines included in each of said bit line pairs for dropping the power source potential generated in said first sense amplifiers by the threshold voltage into said first potential and for amplifying the potential of the other of the bit lines included in the connected bit line pair to attain said first potential; and a plurality of equalizing means installed corresponding to each of said bit line pairs for equalizing said first potential generated to each of the bit lines included in the corresponding bit line pair and said ground potential into intermediate potential between them.

Claim 15

A semiconductor memory device comprising: a plurality of memory cells each comprising N-channel MOS first transistor and a capacitor, said capacitor holding one of first potential and ground potential, said memory cells being arranged in plural rows and plural columns; a plurality of word lines installed corresponding to each row of the memory cells and used to select the memory cells of each row; a plurality of bit line pairs installed corresponding to every of said bit line pairs of the memory cells, the bit lines included in each column being connected to a first transistor each of the corresponding memory cells; a plurality of first sense amplifiers connected to each of said bit line pairs for generating a potential equal to a power source potential; a plurality of second sense amplifiers connected to each of said bit line pairs for amplifying the potential of one of the bit lines included in the connected bit line pair into the ground potential; a plurality of N-channel MOS second transistors each connected between each of said first sense amplifiers and each of the bit lines included in each of said bit line pairs for dropping the power source potential generated in said first sense amplifiers by the threshold voltage into said first potential and for amplifying the potential of the other of the bit lines included in the connected bit line pair to attain said first potential; and a plurality of equalizing means installed corresponding to each of said bit line pairs for equalizing said first potential generated to each of the bit lines included in the corresponding bit line pair and said ground potential into intermediate potential between them.

Claim 16

A semiconductor memory device as set forth in claim 12, wherein the threshold voltage of said first transistor is equal to the threshold voltage of said second transistor, and said power source potential is supplied to gate of said first transistor.

Claim 19

A semiconductor memory device comprising: a bit line pair composed of a first portion and a second portion; a plurality of memory cells connected to each bit line of the bit line pair of said first portion; first potential generating means connected to each of the bit lines of the bit line pair of said second portion for generating a first potential in response to potential on the bit lines of the bit line pair of said second portion and for supplying a first bit line of the bit line pair of said second portion with said first potential; second potential generating means connected to each of bit lines of the bit line pair of said second portion for generating second potential less than the first potential in response to potential on the bit lines of the bit line pair of said second portion and for supplying a second bit line of the bit line pair of said second portion with the second potential; and potential control means connected in series on each of the bit lines of the bit line pair between said first portion and said second portion of said bit line pair for attenuating and transferring said first potential supplied to said first bit line of the bit line pair of said second portion onto one bit line of the bit line pair of said first portion, said attenuated and transferred potential being larger than said second potential.

Claim 20

A semiconductor memory device comprising: a bit line pair composed of a first portion and a second portion; a plurality of memory cells connected to each bit line of the bit line pair of said first portion; first potential generating means connected to each of the bit lines of the bit line pair of said second portion for generating a first potential in response to potential on the bit lines of the bit line pair of said second portion and for supplying a first bit line of the bit line pair of said second portion with said first potential; second potential generating means connected to each of bit lines of the bit line pair of said second portion for generating second potential less than the first potential in response to potential on the bit lines of the bit line pair of said second portion and for supplying a second bit line of the bit line pair of said second portion with the second potential; and potential control means connected in series on each of the bit lines of the bit line pair between said first portion and said second portion of said bit line pair for attenuating and transferring said first potential supplied to said first bit line of the bit line pair of said second portion onto one bit line of the bit line pair of said first portion, said attenuated and transferred potential being larger than said second potential.

Claim 21

A semiconductor memory device as set forth in claim 1, wherein said first potential generating means is a P-type sense amplifier, said second potential generating means is an N-type sense amplifier, said potential control means is an N-channel MOS transistor having a threshold voltage, and said first potential is attenuated to a third potential equal in value to a difference between said threshold voltage and said first potential.

Claim 22

A semiconductor memory device as set forth in claim 2, wherein each of said memory cells holds one of said second potential and said third potential.