US5019970A
Expired / Lapsed
US
⏱️ 0.0 years remaining
IC card
Assignee: Mitsubishi Electric Corp
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Filing: 1988-11-28
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Granted: 1991-05-28
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Expires: 2008-11-28
Abstract
Abstract An IC card includes an addressable CPU having a memory space including a special area including a first plurality of memory addresses which are addressable with a short instruction word, first and second memories in which test and application programs are stored, respectively, a bus which connects the CPU and the first and second memories, a first selection circuit for forming a first memory mapping arrangement in which at least a portion of the first memory is superimposed on the special area, a second selection circuit for forming a second memory mapping arrangement in which at least a portion of the second memory is superimposed on the special area, a detection circuit for detecting the execution of the test program or the application program, and a changeover circuit arranged to selectively operate the first and second selection circuits according to the result of detection executed by the detection circuit. The above-described arrangement makes it possible to effectively use the special area to efficiently execute either the application program or the test program.
Inventors
- 👤 Atsuo Yamaguchi
- 👤 Kenichi Takahira
- 👤 Shigeru Furuta
- 👤 Takesi Inoue
- 👤 Toshiyuki Matsubara
- 👤 Shuzo Fujioka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:06
CPC Classifications
G; G07; G07F; G07F7/00; G07F7/08; G07F7/10; G07F7/1008; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G06Q; G06Q20/00; G06Q20/30; G06Q20/34; G06Q20/341; G06Q20/357
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
383 words
An IC card comprising: a CPU having an addressable memory space including a plurality of memory addresses, each memory address being uniquely addressable by means of at least one of a plurality of instruction words, each instruction word having a predetermined length, the addressable memory space including a special page including a plurality of special memory addresses which are addressable by instruction words which are shorter in length than the instruction words used for addressing memory addresses not included in the special page; a first memory for storing a first program for execution by said CPU, said first memory including a starting address in which is stored a first instruction of the first program; a second memory for storing a second program for execution by said CPU, said second memory including a starting address in which is stored a first instruction of the second program and a predetermined address, wherein said CPU is programmed to address the predetermined address prior to executing the second program; a bus connecting said CPU to said first and second memories; selection means connected to said bus and said first and second memories and having a first state and a second state and for enabling, in the first state, said first memory when said CPU addresses a first range of memory addresses and said second memory when said CPU addresses a second range of memory addresses, and for enabling, in the second state, said first memory when said CPU addresses a third range of memory addresses and said second memory when said CPU addresses a fourth range of memory addresses, wherein the first and fourth ranges at least partially include the special page and said selection means is normally in the first state; detection means connected to said bus for detecting when said CPU addresses the predetermined address of said second memory, thereby indicating that said CPU is about to execute the second program, and for producing a changeover signal in response thereto; and changeover means connected to said detection means and said first and second memories and connected for switching said selection means to the second state from the first state in response to the changeover signal, whereby the second program in said second memory may be addressed in the special page by a shorter instruction word.
Claim 2
Dependent Claim
383 words
An IC card comprising: a CPU having an addressable memory space including a plurality of memory addresses, each memory address being uniquely addressable by means of at least one of a plurality of instruction words, each instruction word having a predetermined length, the addressable memory space including a special page including a plurality of special memory addresses which are addressable by instruction words which are shorter in length than the instruction words used for addressing memory addresses not included in the special page; a first memory for storing a first program for execution by said CPU, said first memory including a starting address in which is stored a first instruction of the first program; a second memory for storing a second program for execution by said CPU, said second memory including a starting address in which is stored a first instruction of the second program and a predetermined address, wherein said CPU is programmed to address the predetermined address prior to executing the second program; a bus connecting said CPU to said first and second memories; selection means connected to said bus and said first and second memories and having a first state and a second state and for enabling, in the first state, said first memory when said CPU addresses a first range of memory addresses and said second memory when said CPU addresses a second range of memory addresses, and for enabling, in the second state, said first memory when said CPU addresses a third range of memory addresses and said second memory when said CPU addresses a fourth range of memory addresses, wherein the first and fourth ranges at least partially include the special page and said selection means is normally in the first state; detection means connected to said bus for detecting when said CPU addresses the predetermined address of said second memory, thereby indicating that said CPU is about to execute the second program, and for producing a changeover signal in response thereto; and changeover means connected to said detection means and said first and second memories and connected for switching said selection means to the second state from the first state in response to the changeover signal, whereby the second program in said second memory may be addressed in the special page by a shorter instruction word.
Claim 3
Dependent Claim
43 words
An IC card according to claim 1 wherein the predetermined address of said second memory stores the starting address of the second program, and said CPU is programmed to read the starting address of the second program prior to executing the second program.
References Cited (Backward Citations)
US4709137A
Cited
US4646298A
Cited
US4650975A
Cited
US4829169A
Cited
US4755660A
Cited
US4748320A
Cited
US4816656A
Cited
US4839506A
Cited
US4804825A
Cited
US4949298A
Cited
US4777355A
Cited
US4930129A
Cited
US4960982A
Cited
US4965802A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-27 | 1994-11-26 | 1995-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-27 | 1998-11-26 | 1999-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-27 | 2002-11-26 | 2003-05-28 | $7700.00 | Window Closed / Lapsed |