Apparatus and method for reducing flickering in a still video frame in a digital image processing system

Claim 1

An apparatus for reducing flickering in a video still frame produced from first and second video fields in a digital image processing system, comprising: analog-to-digital (A/D) converter means for converting an input analog video signal into digital video data at a predetermined sampling frequency, said A/D converter means receiving as its input analog video signal first and second analog video field signal constituents of input analog video frames in succession and converting same respectively into corresponding first digital video field data and second digital video field data constituents of corresponding digital video frames; image memory means having a data input operably coupled with a data output of said A/D converter means, said image memory also having a read-write address (R/W ADDR) control terminal, for storing and outputting data of successive first and second digital video fields of corresponding digital video frames under control of said R/W ADDR control terminal; field memory means having a data input operably connected via a first data path (L1) with a data output of said image memory means and also having a R/W ADDR control terminal, for storing and outputting data of a first digital video field of a digital video frame under control of said R/W ADDR control terminal of said field memory means; adder means having a first adder input operably connected via a secnd data path (L3) with a data output of said image memory means for receiving data of a second digital video field of a digital video frame output therefrom, and a second adder input operably connected with a data output of said field memory means for receiving data of said first digital video field of said digital video frame therefrom, said adder means furrther having a control terminal, for adding said data of said first digital video field data with said data of said second digital video field to produce the sum thereof; divider means operably connected with a data output of said adder representing said sum means and also having a control terminal, for dividing the added data of said first and second digital video fields output from said adder means by two to produce an averaged data of said first digital video field data and said second digital video field data therefrom; selector means having a first data input operably connected via a third data path (L2) with a data output of said image memory means for receiving said first digital video field data output therefrom, a second data input operably connected with a data output of said divider means for receiving said averaged data of said first and second digital video field data output therefrom, and also having a data output and a control terminal, for successively coupling said first digital video data appearing on said first data input and said averaged data of said first and second digital video fields appearing on said second data input thereof to said data output thereof under control of said control terminal thereof; digital-to-analog (D/A) converter means operably connected with the data output of said selector means, for converting, at said predetermined sampling frequency, said successively output first digital video field data and said averaged data of said first and second digital video fields into respective first and second analog video field signal constituents of an analog video frame signal output; and controller means operably connected with said respective R/W ADDR control terminals of said image memory means and said field memory means and with said respective control terminals of said adder means, said divider means and said selector means, firstly, for addressing said image memory means for causing said image memory means to store data of each first and second digital video field of each digital video frame and for causing said image memory means to read-out data of each said first digital video field of each said digital video frame to said data input of said field memory means via said first data path (L1) and at the same time to said first data input of said selector means via said third data path (L2) and, at the same time, for addressing said field memory means for causing said field memory means to store said data of said first digital video field read-out from said image memory means, and, at the same time, for causing said selector means to couple said read-out first digital video field data from said image memory means via said third data path (L2) and said first data input and data output of said selector means for supplying data of a first digital video field of a digital video still frame to said D/A converter means; secondly, for addressing said image memory means to read-out said stored data of said second digital video field via said second path (L3) to said first data input of said adder means, and for addressing said field memory means for causing said field memory means to read-out said stored data of said first digital video field to said second data input of said adder means; thirdly, for causing said adder means to add said data of said first and second digital video fields input thereto for producing the sum thereof; and fourthly, for causing said divider means to divide said sum of said data of said first and second digital video fields by two for producing the averaged data thereof, and, at the same time, for causing said selector means to couple said averaged data of said first and second digital video fields via its second data input and data output for supplying data of a second digital video field of a digital video still frame to said D/A converter means.

Claim 2

An apparatus for reducing flickering in a video still frame produced from first and second video fields in a digital image processing system, comprising: analog-to-digital (A/D) converter means for converting an input analog video signal into digital video data at a predetermined sampling frequency, said A/D converter means receiving as its input analog video signal first and second analog video field signal constituents of input analog video frames in succession and converting same respectively into corresponding first digital video field data and second digital video field data constituents of corresponding digital video frames; image memory means having a data input operably coupled with a data output of said A/D converter means, said image memory also having a read-write address (R/W ADDR) control terminal, for storing and outputting data of successive first and second digital video fields of corresponding digital video frames under control of said R/W ADDR control terminal; field memory means having a data input operably connected via a first data path (L1) with a data output of said image memory means and also having a R/W ADDR control terminal, for storing and outputting data of a first digital video field of a digital video frame under control of said R/W ADDR control terminal of said field memory means; adder means having a first adder input operably connected via a secnd data path (L3) with a data output of said image memory means for receiving data of a second digital video field of a digital video frame output therefrom, and a second adder input operably connected with a data output of said field memory means for receiving data of said first digital video field of said digital video frame therefrom, said adder means furrther having a control terminal, for adding said data of said first digital video field data with said data of said second digital video field to produce the sum thereof; divider means operably connected with a data output of said adder representing said sum means and also having a control terminal, for dividing the added data of said first and second digital video fields output from said adder means by two to produce an averaged data of said first digital video field data and said second digital video field data therefrom; selector means having a first data input operably connected via a third data path (L2) with a data output of said image memory means for receiving said first digital video field data output therefrom, a second data input operably connected with a data output of said divider means for receiving said averaged data of said first and second digital video field data output therefrom, and also having a data output and a control terminal, for successively coupling said first digital video data appearing on said first data input and said averaged data of said first and second digital video fields appearing on said second data input thereof to said data output thereof under control of said control terminal thereof; digital-to-analog (D/A) converter means operably connected with the data output of said selector means, for converting, at said predetermined sampling frequency, said successively output first digital video field data and said averaged data of said first and second digital video fields into respective first and second analog video field signal constituents of an analog video frame signal output; and controller means operably connected with said respective R/W ADDR control terminals of said image memory means and said field memory means and with said respective control terminals of said adder means, said divider means and said selector means, firstly, for addressing said image memory means for causing said image memory means to store data of each first and second digital video field of each digital video frame and for causing said image memory means to read-out data of each said first digital video field of each said digital video frame to said data input of said field memory means via said first data path (L1) and at the same time to said first data input of said selector means via said third data path (L2) and, at the same time, for addressing said field memory means for causing said field memory means to store said data of said first digital video field read-out from said image memory means, and, at the same time, for causing said selector means to couple said read-out first digital video field data from said image memory means via said third data path (L2) and said first data input and data output of said selector means for supplying data of a first digital video field of a digital video still frame to said D/A converter means; secondly, for addressing said image memory means to read-out said stored data of said second digital video field via said second path (L3) to said first data input of said adder means, and for addressing said field memory means for causing said field memory means to read-out said stored data of said first digital video field to said second data input of said adder means; thirdly, for causing said adder means to add said data of said first and second digital video fields input thereto for producing the sum thereof; and fourthly, for causing said divider means to divide said sum of said data of said first and second digital video fields by two for producing the averaged data thereof, and, at the same time, for causing said selector means to couple said averaged data of said first and second digital video fields via its second data input and data output for supplying data of a second digital video field of a digital video still frame to said D/A converter means.

Claim 3

A method for reducing flickering in a video still frame produced from first and second video fields in a digital image processing system, comprising; converting an input analog video signal comprising first and second analog video field signal constituents of input analog video frames in succession respectively into corresponding first digital video field data and second digital video field data constituents of corresponding digital video frames; storing data of said first and second digital video fields of a digital video frame in an image memory; reading-out said stored data of said first digital video field of said digital video frame from said image memory; converting said read-out data of said first digital video field of said digital video frame into a first analog video field signal constituent of an analog still video frame; storing said read-out data of said first digital video field in field memory; reading-out said stored data of said first digital video field from said field memory; reading-out said stored data of said second digital video field from said image memory; adding said read-out data of said first digital video field from said field memory and said read-out data of said second digital video field from said image memory, for producing the digital sum thereof; dividing the sum of said data of said first digital video field and said data of said second digital video field by two, for producing the digital average thereof; and converting the digital average of said soft data of said first and second digital video fields into a second analog video field signal constituent of an analog still video frame.

Claim 4

A method for reducing flickering in a video still frame produced from first and second video fields in a digital image processing system, comprising; converting an input analog video signal comprising first and second analog video field signal constituents of input analog video frames in succession respectively into corresponding first digital video field data and second digital video field data constituents of corresponding digital video frames; storing data of said first and second digital video fields of a digital video frame in an image memory; reading-out said stored data of said first digital video field of said digital video frame from said image memory; converting said read-out data of said first digital video field of said digital video frame into a first analog video field signal constituent of an analog still video frame; storing said read-out data of said first digital video field in field memory; reading-out said stored data of said first digital video field from said field memory; reading-out said stored data of said second digital video field from said image memory; adding said read-out data of said first digital video field from said field memory and said read-out data of said second digital video field from said image memory, for producing the digital sum thereof; dividing the sum of said data of said first digital video field and said data of said second digital video field by two, for producing the digital average thereof; and converting the digital average of said soft data of said first and second digital video fields into a second analog video field signal constituent of an analog still video frame.

Claim 5

An apparatus for reducing flickering in a video still frame produced from first and second video fields in a digital image processing system, comprising: image memory means having a read-write address (R/W ADDR) control terminal, for storing and outputting data of successive first and second digital video fields of corresponding digital video frames under control of said R/W ADDR control terminal; field memory means having a data input operably connected via a first data path (L1) with a data output of said image memory means and also having a R/W ADDR control terminal, for storing and outputting data of a first digital video field of a digital video frame under control of said R/W ADDR control terminal of said field memory means; adder means having a first adder input operably connected via a second data path (L3) with a data output of said image memory means for receiving data of a second digital video field of a digital video frame output therefrom, and a second adder input operably connected with a data output of said field memory means for receiving data of said first digital video field of said digital video frame therefrom, said adder means further having a control terminal, for adding said data of said first digital video field data with said data of said second digital video field to produce the sum thereof; divider means operably connected with a data output of said adder means and also having a control terminal, for dividing the added data representing said sum of said first and second digital video fields output from said adder means by two to produce an averaged data of said first digital video field data and said second digital video field data therefrom; selector means having a first data input operably connected via a third data path (L2) with a data output of said image memory means for receiving said first digital video filed data output therefrom, a second data input operably connected with a data output of said divider means for receiving said averaged data of said first and second digital video field data output therefrom, and also having a data output and a control terminal, for successively coupling said first digital video data appearing on said first data input and said averaged data of said first and second digital video fields appearing on said second data input thereof to said data output thereof under control of said control terminal thereof; and controller means operably connected with said respective R/W ADDR control terminals of said image memory means and said field memory means and with said respective control terminals of said adder means, said divider means and said selector means, firstly, for addressing said image memory means for causing said image memory means to store data of each first and second digital video field of each digital video frame and for causing said image memory means to read-out data of each said first digital video field of each said digital video frame to said data input of said field memory means via said first data path (L1) and at the same time to said first data input of said selector means via said third data path (L2) and, at the same time, for addressing said field memory means for causing said field memory means to store said data of said first digital video field read-out from said image memory means, and, at the same time, for causing said selector means to couple said read-out first digital video field data from said image memory means via said third data path (L2) and said first data input and data output of said selector means for supplying a data output of a first digital video field of a digital video still frame; secondly, for addressing said image memory means to read-out said stored data of said second digital video field via said second data path (L3) to said first data input of said adder means, and for addressing said field memory means for causing said field memory means to read-out said stored data of said first digital video field to said second data input of said adder means; thirdly, for causing said adder means to add said data of said first and second digital video fields input thereto for producing said sum thereof; and fourthly, for causing said divider means to divide said sum of said data of said first and second digital video fields by two for producing said averaged data thereof, and, at the same time, for causing said selector means to couple said averaged data of said first and second digital video fields via its second data input and data output for supplying a data output of a second digital video field of a digital video still frame.

Claim 6

An apparatus for reducing flickering in a video still frame produced from first and second video fields in a digital image processing system, comprising: image memory means having a read-write address (R/W ADDR) control terminal, for storing and outputting data of successive first and second digital video fields of corresponding digital video frames under control of said R/W ADDR control terminal; field memory means having a data input operably connected via a first data path (L1) with a data output of said image memory means and also having a R/W ADDR control terminal, for storing and outputting data of a first digital video field of a digital video frame under control of said R/W ADDR control terminal of said field memory means; adder means having a first adder input operably connected via a second data path (L3) with a data output of said image memory means for receiving data of a second digital video field of a digital video frame output therefrom, and a second adder input operably connected with a data output of said field memory means for receiving data of said first digital video field of said digital video frame therefrom, said adder means further having a control terminal, for adding said data of said first digital video field data with said data of said second digital video field to produce the sum thereof; divider means operably connected with a data output of said adder means and also having a control terminal, for dividing the added data representing said sum of said first and second digital video fields output from said adder means by two to produce an averaged data of said first digital video field data and said second digital video field data therefrom; selector means having a first data input operably connected via a third data path (L2) with a data output of said image memory means for receiving said first digital video filed data output therefrom, a second data input operably connected with a data output of said divider means for receiving said averaged data of said first and second digital video field data output therefrom, and also having a data output and a control terminal, for successively coupling said first digital video data appearing on said first data input and said averaged data of said first and second digital video fields appearing on said second data input thereof to said data output thereof under control of said control terminal thereof; and controller means operably connected with said respective R/W ADDR control terminals of said image memory means and said field memory means and with said respective control terminals of said adder means, said divider means and said selector means, firstly, for addressing said image memory means for causing said image memory means to store data of each first and second digital video field of each digital video frame and for causing said image memory means to read-out data of each said first digital video field of each said digital video frame to said data input of said field memory means via said first data path (L1) and at the same time to said first data input of said selector means via said third data path (L2) and, at the same time, for addressing said field memory means for causing said field memory means to store said data of said first digital video field read-out from said image memory means, and, at the same time, for causing said selector means to couple said read-out first digital video field data from said image memory means via said third data path (L2) and said first data input and data output of said selector means for supplying a data output of a first digital video field of a digital video still frame; secondly, for addressing said image memory means to read-out said stored data of said second digital video field via said second data path (L3) to said first data input of said adder means, and for addressing said field memory means for causing said field memory means to read-out said stored data of said first digital video field to said second data input of said adder means; thirdly, for causing said adder means to add said data of said first and second digital video fields input thereto for producing said sum thereof; and fourthly, for causing said divider means to divide said sum of said data of said first and second digital video fields by two for producing said averaged data thereof, and, at the same time, for causing said selector means to couple said averaged data of said first and second digital video fields via its second data input and data output for supplying a data output of a second digital video field of a digital video still frame.