Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
196 words
A system for the contactless exchange of data between a transceiver and a passive data carrier, said data carrier comprising at least one digital memory means and at least one digital control device for controlling said memory means, and wherein the data carrier has a single-coil receiver circuit connected to a controllable switch means and, in operation, in response to an electromagnetic a.c. field generated by a transceiver, provides via at least one rectifier means supply power to active components of the data carrier as well as clock signals for controlling digital components of the data carrier, characterized in that the transceiver comprises a modulator for the amplitude modulation of said a.c. field received by said coil receiver circuit and that the control device, connected to said coil through a two-branch voltage divider so the voltage at the clock signal input is higher than at the data signal input, has two inputs for receiving clock signals and data signals from the receiver circuit and includes level detectors cooperating with said inputs and arranged to allow the passage of an input signal voltage exceeding a pre-determined value as a valid input signal pulse to said memory means.
Claim 2
Independent Claim
196 words
A system for the contactless exchange of data between a transceiver and a passive data carrier, said data carrier comprising at least one digital memory means and at least one digital control device for controlling said memory means, and wherein the data carrier has a single-coil receiver circuit connected to a controllable switch means and, in operation, in response to an electromagnetic a.c. field generated by a transceiver, provides via at least one rectifier means supply power to active components of the data carrier as well as clock signals for controlling digital components of the data carrier, characterized in that the transceiver comprises a modulator for the amplitude modulation of said a.c. field received by said coil receiver circuit and that the control device, connected to said coil through a two-branch voltage divider so the voltage at the clock signal input is higher than at the data signal input, has two inputs for receiving clock signals and data signals from the receiver circuit and includes level detectors cooperating with said inputs and arranged to allow the passage of an input signal voltage exceeding a pre-determined value as a valid input signal pulse to said memory means.
Claim 3
Dependent Claim
17 words
A system as claimed in claim 1, characterized in that the memory means is a non-volatile memory.
Claim 4
Dependent Claim
22 words
A system as claimed in claim 1, characterized in that the memory means is an EEPROM designed according to the IIC architecture.
Claim 5
Dependent Claim
34 words
A system as claimed in claim 3, characterized in that the memory means is connected to the digital control device via an IIC bus, which comprises a serial data line and a clock line.
Claim 6
Dependent Claim
62 words
A system as claimed in claim 1, characterized in that the voltage which, in operation, prevails across the coil is supplied to the voltage divider connected parallel to a first single-acting rectifier means (D1), and that the switch means is connected to the coil in series with a second single-acting rectifier means (D2) acting oppositely to said first single-acting rectifier means (D1).
Claim 7
Dependent Claim
23 words
A system as claimed in claim 1, characterized in that the switch means has a control input connected to the digital control device.
Claim 8
Dependent Claim
29 words
A system as claimed in claim 1, characterized in that the modulator of the transceiver is arranged, in operation, to vary the modulation per period of the a.c. field.
Claim 9
Independent Claim
277 words
A system for the contactless exchange of data between a transceiver and a passive data carrier, said data carrier comprising at least one digital memory means and at least one digital control device for controlling said memory means, and wherein the data carrier has a single-coil receiver circuit connected to a controllable switch means and, in operation, in response to an electromagnetic a.c. field generated by a transceiver, provides via at least one rectifier means supply power to active components of the data carrier as well as clock signals for controlling digital components of the data carrier, characterized in that the transceiver comprises a modulator for the amplitude modulation of said a.c. field received by said coil receiver circuit and that the control device, connected to said coil through a two-branch voltage divider so the voltage at the clock signal input is higher than at the data signal input has two inputs for receiving clock signals and data signals from the receiver circuit and includes level detectors cooperating with said inputs and arranged to allow the passage of an input signal voltage exceeding a pre-determined value as a valid input signal pulse and further characterized in that the memory means is an EEPROM designed according to the IIC architecture and is connected to the digital control device via an ICC bus, which comprises a serial data line and a clock line and the control device is arranged to form a control signal for the switch means with a frequency which is a submultiple of the frequency of the a.c. field, and whose phase relative to the a.c. field depends on the status of the serial data line.
Claim 10
Independent Claim
277 words
A system for the contactless exchange of data between a transceiver and a passive data carrier, said data carrier comprising at least one digital memory means and at least one digital control device for controlling said memory means, and wherein the data carrier has a single-coil receiver circuit connected to a controllable switch means and, in operation, in response to an electromagnetic a.c. field generated by a transceiver, provides via at least one rectifier means supply power to active components of the data carrier as well as clock signals for controlling digital components of the data carrier, characterized in that the transceiver comprises a modulator for the amplitude modulation of said a.c. field received by said coil receiver circuit and that the control device, connected to said coil through a two-branch voltage divider so the voltage at the clock signal input is higher than at the data signal input has two inputs for receiving clock signals and data signals from the receiver circuit and includes level detectors cooperating with said inputs and arranged to allow the passage of an input signal voltage exceeding a pre-determined value as a valid input signal pulse and further characterized in that the memory means is an EEPROM designed according to the IIC architecture and is connected to the digital control device via an ICC bus, which comprises a serial data line and a clock line and the control device is arranged to form a control signal for the switch means with a frequency which is a submultiple of the frequency of the a.c. field, and whose phase relative to the a.c. field depends on the status of the serial data line.
Claim 11
Dependent Claim
25 words
A system as claimed in claim 8, further characterized in that the frequency of the control signal is half the frequency of the a.c. field.
Claim 12
Independent Claim
314 words
A system for the contactless exchange of data between a transceiver and a passive data carrier, said data carrier comprising at least one digital memory means and at least one digital control device for controlling said memory means, and wherein the data carrier has a single-coil receiver circuit connected to a controllable switch means and, in operation, in response to an electromagnetic a.c. field generated by a transceiver, provides via at least one rectifier means supply power to active components of the data carrier as well as clock signals for controlling digital components of the data carrier, characterized in that the transceiver comprises a modulator for the amplitude modulation of said a.c. field received by said coil receiver circuit and that the control device, connected to said coil through a two-branch voltage divider so the voltage at the clock signal input is higher than at the data signal input, has two inputs for receiving clock signals and data signals from the receiver circuit and includes level detectors cooperating with said inputs and arranged to allow the passage of an input signal voltage exceeding a pre-determined value as valid input signal pulse and further characterized in that the memory means is an EEPROM designed according to the IIC architecture and is connected to the digital control device via an ICC bus, which comprises a serial data line and a clock line and the control device is arranged to form a control signal for the switch means with a frequency which is a submultiple of the frequency of the a.c. field, and whose phase relative to the a.c. field depends on the status of the serial data line; and the control device is arranged, each time after the receipt of a pre-determined number of bits via the data input, to feed back the status of the serial data line by corresponding control of the switch means.
Claim 13
Independent Claim
314 words
A system for the contactless exchange of data between a transceiver and a passive data carrier, said data carrier comprising at least one digital memory means and at least one digital control device for controlling said memory means, and wherein the data carrier has a single-coil receiver circuit connected to a controllable switch means and, in operation, in response to an electromagnetic a.c. field generated by a transceiver, provides via at least one rectifier means supply power to active components of the data carrier as well as clock signals for controlling digital components of the data carrier, characterized in that the transceiver comprises a modulator for the amplitude modulation of said a.c. field received by said coil receiver circuit and that the control device, connected to said coil through a two-branch voltage divider so the voltage at the clock signal input is higher than at the data signal input, has two inputs for receiving clock signals and data signals from the receiver circuit and includes level detectors cooperating with said inputs and arranged to allow the passage of an input signal voltage exceeding a pre-determined value as valid input signal pulse and further characterized in that the memory means is an EEPROM designed according to the IIC architecture and is connected to the digital control device via an ICC bus, which comprises a serial data line and a clock line and the control device is arranged to form a control signal for the switch means with a frequency which is a submultiple of the frequency of the a.c. field, and whose phase relative to the a.c. field depends on the status of the serial data line; and the control device is arranged, each time after the receipt of a pre-determined number of bits via the data input, to feed back the status of the serial data line by corresponding control of the switch means.
Claim 14
Dependent Claim
38 words
A system as claimed in claim 8, further characterized in that the detector of the transceiver is arranged to reconstruct the control signal and to compare the phase of the reconstructed signal with that of the a.c. field.
Claim 15
Dependent Claim
40 words
A system as claimed in claim 8, further characterized in that the detector of the transceiver is arranged to determine the amplitude of successive peaks of the a.c. field and from it to determine the phase of the control signal.
Claim 16
Dependent Claim
51 words
A system as claimed in claim 8, further characterized in that the detector of the transceiver is arranged to determine a progressive average of the amplitude of the odd and the even peaks of the a.c. field and compare these with each other to determine the phase of the control signal.
Claim 17
Independent Claim
209 words
A system for the contactless exchange of data between a transceiver and a passive data carrier, said data carrier comprising at least one digital memory means and at least one digital control device for controlling said memory means, and wherein the data carrier has a single-coil receiver circuit connected to a controllable switch means and, in operation, in response to an electromagnetic a.c. field generated by a transceiver, provides via at least one rectifier means supply power to active components of the data carrier as well as clock signals for controlling digital components of the data carrier, characterized in that the transceiver comprises a modulator for the amplitude modulation of said a.c. field received by said coil receiver circuit and that the control device, connected to said coil through a two branch voltage divider so the voltage at the clock signal input is higher than at the data signal input, has two inputs for receiving clock signals and data signals from the receiver circuit and includes level detectors cooperating with said inputs and arranged to allow the passage of an input signal voltage exceeding a pre-determined value as a valid input signal pulse to said memory means and characterized by at least one sensor connector to the control device.
Claim 18
Independent Claim
209 words
A system for the contactless exchange of data between a transceiver and a passive data carrier, said data carrier comprising at least one digital memory means and at least one digital control device for controlling said memory means, and wherein the data carrier has a single-coil receiver circuit connected to a controllable switch means and, in operation, in response to an electromagnetic a.c. field generated by a transceiver, provides via at least one rectifier means supply power to active components of the data carrier as well as clock signals for controlling digital components of the data carrier, characterized in that the transceiver comprises a modulator for the amplitude modulation of said a.c. field received by said coil receiver circuit and that the control device, connected to said coil through a two branch voltage divider so the voltage at the clock signal input is higher than at the data signal input, has two inputs for receiving clock signals and data signals from the receiver circuit and includes level detectors cooperating with said inputs and arranged to allow the passage of an input signal voltage exceeding a pre-determined value as a valid input signal pulse to said memory means and characterized by at least one sensor connector to the control device.
Claim 19
Dependent Claim
24 words
A system as claimed in claim 14, further characterized in that the sensor has built up a serial interface according to the IIC architecture.
Claim 20
Dependent Claim
203 words
A data carrier for use in a system for the contactless exchange of data between a transceiver and a passive data carrier, said data carrier comprising at least one digital memory means and at least one digital control device for controlling said memory means, and wherein the data carrier has a single-coil receiver circuit connected to a controllable switch means and, in operation, in response to an electromagnetic a.c. field generated by a transceiver, provides via at least one rectifier means supply power to active components of the data carrier as well as clock signals for controlling digital components of the data carrier, characterized in that the transceiver comprises a modulator for the amplitude modulation of said a.c. field received by said coil receiver circuit and that the control device, connected to said coil through a two branch voltage divider so the voltage at the clock signal input is higher than at the data signal input, has two inputs for receiving clock signals and data signals from the receiver circuit and includes level detectors cooperating with said inputs and arranged to allow the passage of an input signal voltage exceeding a pre-determined value as a valid input signal pulse to said memory means.
Claim 21
Dependent Claim
203 words
A data carrier for use in a system for the contactless exchange of data between a transceiver and a passive data carrier, said data carrier comprising at least one digital memory means and at least one digital control device for controlling said memory means, and wherein the data carrier has a single-coil receiver circuit connected to a controllable switch means and, in operation, in response to an electromagnetic a.c. field generated by a transceiver, provides via at least one rectifier means supply power to active components of the data carrier as well as clock signals for controlling digital components of the data carrier, characterized in that the transceiver comprises a modulator for the amplitude modulation of said a.c. field received by said coil receiver circuit and that the control device, connected to said coil through a two branch voltage divider so the voltage at the clock signal input is higher than at the data signal input, has two inputs for receiving clock signals and data signals from the receiver circuit and includes level detectors cooperating with said inputs and arranged to allow the passage of an input signal voltage exceeding a pre-determined value as a valid input signal pulse to said memory means.
Claim 22
Independent Claim
258 words
A system for the contactless exchange of data between a transceiver and a passive data carrier, said data carrier comprising at least one digital memory means and at least one digital control device for controlling said memory means, and wherein the data carrier has a single-coil receiver circuit connected to a controllable switch means and , in operation, in response to an electromagnetic a.c. field generated by a transceiver, provides via at least one rectifier means supply power to active components of the data carrier as well as clock signals for controlling digital components of the data carrier, characterized in that the transceiver comprises a modulator for the amplitude modulation of said a.c. field received by said coil receiver circuit and that the control device, connected to said coil through a two branch voltage divider so the voltage at the clock signal input is higher than at the data signal input, has two inputs for receiving clock signals and data signals from the receiver circuit and includes level detectors cooperating with said inputs and arranged to allow the passage of an input signal voltage exceeding a pre-determined value as a valid input signal pulse to said memory means and further characterized in that the transceiver includes means for varying the transmission power level between zero and a pre-determined maximum value and setting it at a level intermediate the level at which a data carrier just returns signals and a level at which the data carrier no longer perceives any difference between a binary "0" and a binary "1".
Claim 23
Independent Claim
258 words
A system for the contactless exchange of data between a transceiver and a passive data carrier, said data carrier comprising at least one digital memory means and at least one digital control device for controlling said memory means, and wherein the data carrier has a single-coil receiver circuit connected to a controllable switch means and , in operation, in response to an electromagnetic a.c. field generated by a transceiver, provides via at least one rectifier means supply power to active components of the data carrier as well as clock signals for controlling digital components of the data carrier, characterized in that the transceiver comprises a modulator for the amplitude modulation of said a.c. field received by said coil receiver circuit and that the control device, connected to said coil through a two branch voltage divider so the voltage at the clock signal input is higher than at the data signal input, has two inputs for receiving clock signals and data signals from the receiver circuit and includes level detectors cooperating with said inputs and arranged to allow the passage of an input signal voltage exceeding a pre-determined value as a valid input signal pulse to said memory means and further characterized in that the transceiver includes means for varying the transmission power level between zero and a pre-determined maximum value and setting it at a level intermediate the level at which a data carrier just returns signals and a level at which the data carrier no longer perceives any difference between a binary "0" and a binary "1".