US5018101A
Expired / Lapsed
US
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Semiconductor memory
Assignee: Hitachi Ltd
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Filing: 1990-08-31
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Granted: 1991-05-21
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Expires: 2010-08-31
Abstract
Abstract A semiconductor memory wherein an operating mode is selectively set by effecting bonding with respect to predetermined pads provided on a common semiconductor substrate in a predetermined combination or by cutting off predetermined fuse means provided on the common semiconductor substrate in a predetermined combination and a bit pattern is selectively set by changing a part of a photomask applied to the common semiconductor substrate.
Inventors
- 👤 Kazuhiko Kajigaya
- 👤 Hiroaki Kotani
- 👤 Kazuyoshi Oshima
- 👤 Yasuhiro Kasama
- 👤 Shinji Udo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:52
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
127 words
A semiconductor memory having a plurality of operating modes comprising: a plurality of pads which correspond in a predetermined manner to a plurality of output circuits; first connecting means for coupling said output circuits and corresponding pads selectively on the basis of an output bit pattern of said semiconductor memory; a signal generator for delivering control signals for specifying said predetermined one of said operation modes; and a first input pad which corresponds to said signal generator and which serves to couple a predetermined voltage to said signal generator for controlling said signal generator, wherein said first connecting means is provided by a first conductive layer formed on a semiconductor substrate, and wherein said first input pad is connected to said predetermined voltage by effecting wire bonding.
Claim 2
Dependent Claim
127 words
A semiconductor memory having a plurality of operating modes comprising: a plurality of pads which correspond in a predetermined manner to a plurality of output circuits; first connecting means for coupling said output circuits and corresponding pads selectively on the basis of an output bit pattern of said semiconductor memory; a signal generator for delivering control signals for specifying said predetermined one of said operation modes; and a first input pad which corresponds to said signal generator and which serves to couple a predetermined voltage to said signal generator for controlling said signal generator, wherein said first connecting means is provided by a first conductive layer formed on a semiconductor substrate, and wherein said first input pad is connected to said predetermined voltage by effecting wire bonding.
Claim 3
Dependent Claim
69 words
A semiconductor memory according to claim 1, further comprising: a plurality of input circuits being provided which correspond in a predetermined manner to said plurality of pads; and second connecting means for coupling said input circuits and corresponding pads selectively on the basis of said output bit pattern of said semiconductor memory, wherein said second connecting means is provided by a second conductive layer formed on a semiconductor substrate.
Claim 4
Dependent Claim
36 words
A semiconductor memory according to claim 2, further comprising: a second input pad which corresponds to said signal generator and which serves to couple a predetermined voltage to said signal generator for controlling said signal generator.
Claim 5
Dependent Claim
29 words
A semiconductor memory according to claim 3, wherein said first input pad or said second input pad is coupled to a circuit ground potential or a power supply voltage.
Claim 6
Dependent Claim
17 words
A semiconductor memory according to claim 4, wherein said semiconductor memory is a dynamic random access memory.
Claim 7
Dependent Claim
18 words
A semiconductor memory according to claim 4, wherein said semiconductor memory is formed on a common semiconductor substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-05-20 | 1994-11-19 | 1995-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-20 | 1998-11-19 | 1999-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-20 | 2002-11-19 | 2003-05-21 | $7700.00 | Window Closed / Lapsed |