Comparison circuit

Claim 2

A comparison element comprising: first and second inputs; first and second pass transistors connected to the first and second inputs, respectively, and to provide first and second outputs, respectively; first and second cross-over transistors connected to said first and second pass transistors, respectively, said first and second cross-over transistors being connected to said second and first inputs, respectively; said pass transistors and said cross-over transistors being configured to store data at the junctions between said pass transistors and said cross-over transistors as received from the second and first inputs by the first and second cross-over transistors respectively, said first and second pass transistors being configured to compare stored data and comparison data presented on the first and second inputs, respectively, after the stored data, and to indicate, on one output, whether the comparison data is not less than the stored data and, on the other output, whether the comparison data is not greater than the stored data; and first and second diode means, connected to said first and second outputs respectively, said first and second diode means also being connected to a third output and being configured to indicate whether the comparison data matches the stored data, said first and second diode means individually isolating said first and second outputs from said third output.

Claim 3

The comparison element of claim 1, wherein said diode means are effected by transistors configured as diodes.

Claim 4

The comparison element of claim 1, further comprising logic elements coupled to receive the first and second outputs and configured to provide a fourth output to indicate either whether the comparison data is greater than the stored data or whether the comparison data is less than the stored data.

Claim 5

The comparison element of claim 3, wherein the logic elements include an inverter means connected to invert one of the first and second outputs and a NAND circuit connected to receive the other of the first and second outputs and the inverted one output.

Claim 6

A comparison circuit comprising a plurality of comparison elements, each comparison element being configured to provide an output indicating whether an input is not greater than stored data, and output indicating whether an input is not less than stored data, and an output indicating whether an input is equal to stored data, said plurality of comparison elements being arranged in an upper threshold chain and a lower threshold chain, said outputs indicating whether an input is equal to stored data of said comparison elements of said upper threshold chain, being connected to provide an output indicating whether said input data is equal to an upper limit, said outputs indicating whether an input is equal to stored data of said comparison elements of said lower threshold chain, being connected to provide an output indicating whether said input data is equal to a lower limit, an upper limit circuit configured to receive said outputs indicating whether an input is not greater than and whether an input is not less than, of said upper threshold chain and to provide an upper limit output indicating whether an input word is less than said stored upper limit, a lower limit circuit configured to receive said outputs indicating whether an input is not greater than and whether said input is not less than, of said lower threshold chain and to provide a lower limit output indicating whether an input word is greater than said stored lower limit, and a window circuit configured to receive said upper limit output and said lower limit output and to provide a window output indicating whether said input is within said stored upper limit and said stored lower limit.

Claim 7

A comparison circuit comprising a plurality of comparison elements, each comparison element being configured to provide an output indicating whether an input is not greater than stored data, and output indicating whether an input is not less than stored data, and an output indicating whether an input is equal to stored data, said plurality of comparison elements being arranged in an upper threshold chain and a lower threshold chain, said outputs indicating whether an input is equal to stored data of said comparison elements of said upper threshold chain, being connected to provide an output indicating whether said input data is equal to an upper limit, said outputs indicating whether an input is equal to stored data of said comparison elements of said lower threshold chain, being connected to provide an output indicating whether said input data is equal to a lower limit, an upper limit circuit configured to receive said outputs indicating whether an input is not greater than and whether an input is not less than, of said upper threshold chain and to provide an upper limit output indicating whether an input word is less than said stored upper limit, a lower limit circuit configured to receive said outputs indicating whether an input is not greater than and whether said input is not less than, of said lower threshold chain and to provide a lower limit output indicating whether an input word is greater than said stored lower limit, and a window circuit configured to receive said upper limit output and said lower limit output and to provide a window output indicating whether said input is within said stored upper limit and said stored lower limit.

Claim 8

A circuit for determining predetermined relationships between a stored digital data word and an input data word comprising: A. a first word storage device comprising a series of stages each including a memory element that stores a digital data bit, the bits stored in the series of stages defining the stored digital data word, and a comparator responsive to the stored digital data bit and an input digital data bit, the input digital data bits received by the comparators of the series of stages defining the input data word, the comparator transmitting through respective output terminals signals indicating selected value relationships between the values of the stored digital data bit and the input digital signal; and B. a first logic chain connected to said output terminals that generates a signal indicating selected value relationships between the stored digital data word and the input digital data word, C. a second word storage device for transmitting, through respective output terminals, signals indicating the relationship between the values of stored digital data bits comprising a stored digital data word and input data bits comprising the input data word, D. a second logic chain connected to said second word storage device for generating a signal indicating the relationship of the digital data bits stored in said second word storage device and said input data word; and E. a circuit for generating a consolidated output signal in response to signals from said logic chains to determine selected relationships between the digital data words stored in said word storage device and said input data word.

Claim 9

A circuit for determining predetermined relationships between a stored digital data word and an input data word comprising: A. a first word storage device comprising a series of stages each including a memory element that stores a digital data bit, the bits stored in the series of stages defining the stored digital data word, and a comparator responsive to the stored digital data bit and an input digital data bit, the input digital data bits received by the comparators of the series of stages defining the input data word, the comparator transmitting through respective output terminals signals indicating selected value relationships between the values of the stored digital data bit and the input digital signal; and B. a first logic chain connected to said output terminals that generates a signal indicating selected value relationships between the stored digital data word and the input digital data word, C. a second word storage device for transmitting, through respective output terminals, signals indicating the relationship between the values of stored digital data bits comprising a stored digital data word and input data bits comprising the input data word, D. a second logic chain connected to said second word storage device for generating a signal indicating the relationship of the digital data bits stored in said second word storage device and said input data word; and E. a circuit for generating a consolidated output signal in response to signals from said logic chains to determine selected relationships between the digital data words stored in said word storage device and said input data word.

Claim 10

A circuit as defined in claim 6 in which said second word storage device comprises a series of stages each including a memory element that stores a digital data bit, the bits stored in the series of stages defining the stored digital data word, and a comparator responsive to the stored digital data bit and an input digital data bit, the input digital data bits received by the comparators of the series of stages defining the input data word, the comparator transmitting through respective output terminals signals indicating selected value relationships between the values of the stored digital data bit and the input digital signal.

Claim 11

A circuit as defined in claim 7 in which said comparator of said second word storage device comprises a transistor having a control connection comprising said memory element and other connections connected to receive an input signal representing said input digital data bit and to an output terminal, said transistor controlling the coupling of said input signal to the output terminal.

Claim 12

A circuit as defined in claim 8 further comprising a store enabling circuit for enabling the storage of a digital data word in the memory elements comprising said second word storage device.

Claim 13

A circuit as defined in claim 9 in which said store enabling circuit comprises a series of gates, each associated with a memory element, each facilitating the storage of a digital data bit in the associated memory element in response to a store enabling signal.

Claim 14

A circuit as defined in claim 10 in which said each said comparator comprises a transistor having a control connection comprising said memory element, each said gate being connected to the control connection of said respective transistor for facilitating the storage of the digital data bit at said control connection.