Status holding circuit and logic circuit using the same

Claim 2

A status holding circuit, comprising: a status holding transistor having a negative conductance range and having an emitter coupled to a negative power source, a collector and a base coupled to said collector; first and second input terminals to which first and second input signals are applied; a first resistor provided between said first input terminal and the collector of said transistor; a second resistor provided between said second input terminal and the collector of said transistor; and amplifier means, provided between a positive power source and the negative power source, for amplifying an output from the base of said status holding transistor to thereby generate an amplified output signal.

Claim 3

A status holding circuit as claimed in claim 1, wherein said status holding transistor is a resonant-tunneling hot electron transistor.

Claim 4

A status holding circuit as claimed in claim 1, wherein said status holding transistor is a resonant-tunneling bipolar transistor.

Claim 5

A status holding circuit as claimed in claim 1, wherein said status holding circuit further comprises: an emitter resistor connected to the negative power source, and a load resistor connected to the positive power source, wherein said amplifier means comprises an amplifying transistor having: a base directly connected to the base and the collector of said status holding transistor, an emitter coupled to said negative power source through said emitter resistor; and a collector coupled to said positive power source through said load resistor, outputting the amplified output signal.

Claim 6

A status holding circuit as claimed in claim 1, wherein said status holding circuit further comprises: a third resistor connected to the base and the collector of said status holding transistor, a fourth resistor connected to the negative power source, and a load resistor connected to the positive power source, wherein said amplifier means comprises an amplifying transistor having: a base connected to the base and the collector of said status holding transistor through said third resistor and coupled to said negative power source through said fourth resistor, an emitter directly connected to said negative power source, and a collector, coupled to said positive power source through said load resistor, outputting the amplified output signal.

Claim 7

A status holding circuit as claimed in claim 5, wherein said amplifying transistor is a transistor selected from a group consisting of a resonant-tunneling hot electron transistor, a resonant-tunneling bipolar transistor and a normal bipolar transistor.

Claim 8

A status holding circuit as claimed in claim 5, wherein said status holding transistor is of the same type as said second transistor.

Claim 9

A status holding circuit as claimed in claim 1, wherein when the first and second input signals are both logic "0" the amplified output signal is logic "0", and when the first and second input signals are both logic "1", the amplified output signal is logic "1", and when one of the first and second input signals is logic "0" and the other of the first and second input signals is logic "1", the logic status of the amplified output signal obtained is the same as an immediately previous logic status of the amplified output signal.

Claim 10

A status holding circuit as claimed in claim 1, further comprising an emitter follower transistor having: a base coupled to said amplifier means to receive the amplified output signal, a collector coupled to the positive power source, and an emitter through which an emitter follower output signal is drawn.

Claim 11

A status holding circuit as claimed in claim 1, wherein said first resistor and said second resistor have approximately equal resistances.

Claim 12

A logic circuit coupled to positive and negative power sources and receiving first and second input signals, comprising: an exclusive-OR gate having first and second input terminals and an output terminal, the first input signal being applied to said first input terminal; a status holding circuit coupled to the output terminal and the second input terminal of said exclusive-OR gate, said status holding circuit including: a status holding transistor having an emitter coupled to the negative power source, a collector and a base coupled to the collector and producing an output, said status holding transistor having a negative conductance range; a first input terminal coupled to the output terminal of said exclusive-OR gate; a second input terminal to which the second input signal is applied; a first resistor provided between said first input terminal of said status holding circuit and the collector of said status holding transistor; and a second resistor provided between said second input terminal of said status holding circuit and the collector of said status holding transistor; and amplifier means, provided between the positive power source and the negative power source, for amplifying the output from the base of said status holding transistor to thereby generate an amplified output signal applied to the second input terminal of said exclusive-OR gate.

Claim 13

A logic circuit coupled to positive and negative power sources and receiving first and second input signals, comprising: an exclusive-OR gate having first and second input terminals and an output terminal, the first input signal being applied to said first input terminal; a status holding circuit coupled to the output terminal and the second input terminal of said exclusive-OR gate, said status holding circuit including: a status holding transistor having an emitter coupled to the negative power source, a collector and a base coupled to the collector and producing an output, said status holding transistor having a negative conductance range; a first input terminal coupled to the output terminal of said exclusive-OR gate; a second input terminal to which the second input signal is applied; a first resistor provided between said first input terminal of said status holding circuit and the collector of said status holding transistor; and a second resistor provided between said second input terminal of said status holding circuit and the collector of said status holding transistor; and amplifier means, provided between the positive power source and the negative power source, for amplifying the output from the base of said status holding transistor to thereby generate an amplified output signal applied to the second input terminal of said exclusive-OR gate.

Claim 14

A logic circuit as claimed in claim 11, further comprising a NOT gate, wherein the first input terminal of said status holding circuit is coupled to the output terminal of said exclusive-OR gate through said NOT gate so that said exclusive-OR gate and said NOT gate form an exclusive-NOR gate.

Claim 15

A logic circuit as claimed in claim 12, wherein said logic circuit further comprises: a third resistor coupled to the first input terminal of said exclusive-OR gate, a fourth resistor coupled to the negative power source, a fifth resistor coupled to the negative power source, and a sixth resistor coupled to said amplifier means, wherein said exclusive-NOR gate comprises an XOR transistor having: an emitter coupled to the negative power source, a base coupled to said sixth resistor to receive the amplified output from said amplifier means therethrough, coupled to the first input terminal of said exclusive-OR gate through said third resistor and coupled to said negative power source through said fourth resistor, and a collector connected to the first input terminal of said status holding circuit and coupled to the positive power source through said fifth resistor.

Claim 16

A logic circuit as claimed in claim 13, wherein said third and sixth resistors of said exclusive-NOR gate have essentially equal resistances.

Claim 17

A logic circuit as claimed in claim 13, wherein said XOR and status holding transistors respectively provided in said exclusive-NOR gate and said status holding circuit are resonant-tunneling hot electron resistors.

Claim 18

A logic circuit as claimed in claim 13, wherein said XOR and status holding transistors respectively provided in said exclusive-NOR gate and said status holding circuit are resonant-tunneling bipolar resistors.

Claim 19

A logic circuit as claimed in claim 13, wherein said third and sixth resistors each have a resistance smaller than an input resistance of said XOR transistor of said exclusive-NOR

Claim 20

A logic circuit as claimed in claim 11, wherein said logic circuit further comprises: an emitter resistor coupled to the negative power source, and a load resistor coupled to the positive power source, wherein said amplifier means comprises an amplifying transistor having, a base directly connected to the base and collector of said status holding transistor of said status holding circuit, an emitter coupled to said negative power source through said emitter resistor, and a collector, coupled to said positive power source through said load resistor, outputting the amplified output signal.

Claim 21

A logic circuit as claimed in claim 13, wherein said logic circuit further comprises: a seventh resistor connected to the base and the collector of said status holding transistor; a eighth resistor coupled to the positive power source, and a load resistor coupled to the positive power source, wherein said amplifier means comprises an amplification transistor having: a base connected to the base and the collector of said status holding transistor of said status holding circuit through a seventh resistor and coupled to said negative power source through said eighth resistor, an emitter directly connected to the negative power source, and a collector, coupled to the positive power source through said load resistor, outputting the amplified output signal.

Claim 22

A status holding circuit as claimed in claim 11, wherein the first input signal is a clock signal and the second input signal is a data signal to be held by said status holding circuit in accordance with the first input signal.

Claim 23

A status holding circuit as claimed in claim 20, wherein when the clock signal is logic "0", the amplified output signal is unchanging irrespective of the data signal, and when the clock signal is logic "0", the amplified output signal has the logic state of the data signal.

Claim 24

A logic circuit as claimed in claim 11, further comprising an emitter follower transistor having a base coupled to said amplifier means to receive the amplified output signal, a collector coupled to the positive power source, and an emitter through which the amplified output signal is drawn.

Claim 25

A logic circuit as claimed in claim 19, wherein said XOR transistor, said status holding transistor and said amplification transistor respectively provided in said exclusive-NOR gate, said status holding circuit and said amplifier means have the same type.

Claim 26

A logic circuit receiving clock and data signals, comprising: an exclusive-OR gate having a first input terminal receiving the clock signal, a second input terminal and an output terminal; and a status holding circuit having a first input terminal coupled to the output terminal of said exclusive-OR gate, a second input terminal receiving the data signal, and an output terminal coupled to the second input terminal of said exclusive-OR gate, an output signal being drawn from the output terminal of said status holding circuit, said status holding circuit having a hysteresis characteristic wherein when the clock signal is logic "0", the logic state of the output signal is unchanging irrespective of the data signal, and when the clock signal is logic "1", the output signal has a logic state identical to the data signal.

Claim 27

A logic circuit receiving clock and data signals, comprising: an exclusive-OR gate having a first input terminal receiving the clock signal, a second input terminal and an output terminal; and a status holding circuit having a first input terminal coupled to the output terminal of said exclusive-OR gate, a second input terminal receiving the data signal, and an output terminal coupled to the second input terminal of said exclusive-OR gate, an output signal being drawn from the output terminal of said status holding circuit, said status holding circuit having a hysteresis characteristic wherein when the clock signal is logic "0", the logic state of the output signal is unchanging irrespective of the data signal, and when the clock signal is logic "1", the output signal has a logic state identical to the data signal.

Claim 28

A logic circuit receiving clock and data signals, comprising: an exclusive-NOR gate having a first input terminal receiving the clock signal, a second input terminal and an output terminal; and a status holding circuit having a first input terminal coupled to the output terminal of said exclusive-NOR gate, a second input terminal receiving the data signal, and an output terminal coupled to the second input terminal of said exclusive-NOR gate, an output signal being drawn from the output terminal of said status holding circuit, said status holding circuit having a hysteresis characteristic wherein when the clock signal is logic "0", the logic state of the output signal is unchanging irrespective of the data signal, and when the clock signal is logic "1", the output signal has a logic state opposite the data signal.

Claim 29

A logic circuit receiving clock and data signals, comprising: an exclusive-NOR gate having a first input terminal receiving the clock signal, a second input terminal and an output terminal; and a status holding circuit having a first input terminal coupled to the output terminal of said exclusive-NOR gate, a second input terminal receiving the data signal, and an output terminal coupled to the second input terminal of said exclusive-NOR gate, an output signal being drawn from the output terminal of said status holding circuit, said status holding circuit having a hysteresis characteristic wherein when the clock signal is logic "0", the logic state of the output signal is unchanging irrespective of the data signal, and when the clock signal is logic "1", the output signal has a logic state opposite the data signal.