Arrangement for equalizing and demodulating binary continuous-phase angle-modulated data signals with modulation index 0.5

Claim 2

An arrangement for equalizing and demodulating a binary continuous-phase angle-modulated data signal with a modulation index h=0.5 received from a channel, said arrangement comprising: a baseband converter means for producing at its outputs a first pair of baseband quadrature components representing a received modulated data signal containing a binary data signal; a preprocessing means havings inputs coupled to the outputs of the baseband converter means for producing at its outputs a second pair of baseband quadrature components from said first pair by performing a signal processing which corresponds to a phase rotation of the modulated data signal represented by the first pair of baseband quadrature components by progressing in discrete phase steps of 90°, in the same sense, per bit interval of the binary data signal; and an equalizer/detector means, fed by the outputs of said preprocessing means, for recovering said binary data signal.

Claim 3

An arrangement as claimed in claim 1, wherein the equalizer/detector means comprises an adaptive equalizer/detector means having adjusting signal inputs and further comprising a channel estimator means, coupled to the outputs of the baseband converter means, for producing from the first pair of baseband quadrature components an estimation of the instantaneous channel impulse response in the form of a third pair of quadrature components which are coupled to the adjusting signal inputs of the adaptive equalizer/detector means.

Claim 4

An arrangement as claimed in claim 1, wherein the preprocessing means comprises a first preprocessing means, and wherein the equalizer/detector comprises an adaptive equalizer/detector means having adjusting signal inputs and further comprising a channel estimator means, coupled to the outputs of the baseband converter means, for producing from the first pair of baseband quadrature components an estimation of the instantaneous channel impulse response in the form of a third pair of quadrature components which are applied to the adjusting siganl inputs of the adaptive equalizer/detector means via a second preprocessing means, the first and second preprocessing means effecting the same signal processing operations in sychronism with each other.

Claim 5

An arrangement as claimed in claim 1, wherein the preprocessing means comprirse means for selectively conveying the signals at its inputs to its outputs either interchanged or non-interchanged and either inverted or non-inverted in accordance with a cycle of four clock intervals such that in a first clock interval both signals at its inputs are coveyed to its outputs non-interchanged and non-inverted, in a subsequent second clock interval one of the two signals at its inputs is coveyed inverted and the other of the two signals at its inputs is conveyed non-inverted, in a subsequent third clock interval both signals at its inputs are conveyed inverted and in a subsequent fourth clock interval said other of the two siganls at its inputs that was not conveyed inverted in the second clock interval is conveyed inverted, and in the second and fourth clock intervals the signals at its inputs are conveyed interchanged in addition to the described inversions.

Claim 6

An arrangement as claimed in claim 4, wherein the period of duration of a clock interval corresponds to the length of a bit interval of said binary data signal.

Claim 7

An arrangement as claimed in claim 1, wherein the preprocessing means comprises a first inverter whose input is connected to a first of the outputs of the baseband converter means, and a second inverter whose input is connected to a second of the outputs of the baseband converter means such that the first and second of the outputs of the baseband converter means and the outputs of the first and second inverters comprises a set of four outputs, a modulo-4 counter, first and second multiplexers each having its own output and its own series of four inputs connected to said set of four outputs, the order of connection of said set of four outputs to the series of four inputs of said first multiplexer being different from the order of connection of said set of four outputs to the series of four inputs of the second multiplexer, said series of four inputs of the resepective first and second multiplexers being sequentially connected to the output of the respective first and second multiplexer in accordance with a sequence of states of the modulo-4 counter, the outputs of the first and second multiplexers being connected to the inputs of the equalizer/detector means.

Claim 8

An arrangement as claimed in claim 6, wherein the modulo-4 counter is controlled by a frame synchronization signal.

Claim 9

An arrangement as claimed in claim 6, wherein a first of the series of four inputs of the first multiplexer is connected to the first of the outputs of the baseband converter means, a first of the series of four inputs of the second multiplexer is connected to the second of the outputs of the baseband converter means, a second of the series of inputs of the first multiplexer is connected to the output of the second inverter, a second of the series of inputs of the second multiplexer is connected to the first of the outputs of the baseband converter means, a third of the series of inputs of the first multiplexer is connected to the output of the first inverter, a third of the series of inputs of the second multiplexer is connected to the output of the second inverter, a fourth of the series of inputs of the first multiplexer is connected to the second of the outputs of the baseband converter means, and a fourth of the series of inputs of the second multiplexer is connected to the output of the first inverter.

Claim 10

An arrangement as claimed in claim 6, a first of the series of four inputs of the first multiplexer is connected to the first of the outputs of the baseband converter means, a first of the series of four inputs of the second multiplexer is connected to the second of the outputs of the baseband converter means, a second of the series of inputs of the first multiplexer is connected to the second output of the baseband converter, a second of the series of inputs of the second multiplexer is connected to the output of the first inverter, a third of the series of inputs of the first multiplexer is connected to the output of the first inverter, a third of the series of inputs of the second multiplexer is connected to the output of the second inverter, a fourth of the series of inputs of the first multiplexer is connected to the output of the second inverter, and a fourth of the series of inputs of the second multiplexer is connected to the first of the outputs of the baseband converter.

Claim 11

An arrangement as claimed on claim 1, wherein the equalizer/detector means is an equalizer/detector suitable for binary 0°/180° phase-shift keyed modulated data signals.

Claim 12

An arrangement as claimed in claim 1, wherein the equalizer/detector means is an equalizer/detector suitable for binary pulse amplitude modulated data signals.

Claim 13

An arrangement as claimed in claim 2, wherein the preprocessing means comprises means for selectively conveying the singnals at its inputs to its outputs either interchanged or non-interchanged and either inverted or non-inverted in accordance with a cycle of four clock intervals such that in a first clock interval both signals at its inputs are conveyed to its outputs non-interchanged and non-inverted, in a subsequent second clock interval, one of the two signals at its inputs is conveyed inverted and the other of the two signals at its inputs is conveyed non-inverted, in a subsequent third clock interval both signals at its inputs are conveyed inverted and in a subsequent fourth clock interval said other of the two signals at its inputs that was not conveyed inverted in the second clock interval is conveyed inverted, and in the second and fourth clock intervals the signals at its inputs are conveyed interchanged in addition to the described inversions.

Claim 14

An arrangement as claimed in claim 12, wherein the period of duration of a clock interval corresponds to the length of a bit interval of said binary data signal.

Claim 15

An arrangement as claimed in claim 13, wherein the preprocessing means comprises a first inverter whose input is connected to a first of the outputs of the baseband converter means, and a second inverter whose input is connected to a second of the outputs of the baseband converter means such that the first and second of the outputs of the baseband converter means and the outputs of the first and second inverters comprises a set of four outputs, a modulo-4 counter, first and second multiplexers each having its own output and its own series of four inputs connected to said set of four outputs, the order of connection of said set of four outputs to the series of four inputs of said first multiplexer being different from the order of connection of said set of four outputs to the series of four inputs of the second multiplexer, said series of four inputs of the respective first and second multiplexers being sequentially connected to the output of the respective first and second multiplexer in accordance with a sequence of states of the modulo-4 counter and one, the outputs of the first and second multiplexers being connected to the inputs of the equalizer/detector means.

Claim 16

An arrangement as claimed in claim 3, wherein the preprocessing means comprises means for selectively conveying the signals at its inputs to its outputs either interchanged or non-interchanged and either inverted or non-inverted in accordance with a cycle of four clock intervals such that in a first clock interval both signals at its inputs are conveyed to its outputs non-interchanged and non-inverted, in a subsequent second clock interval, one of the two signals at its inputs is conveyed inverted and the other of the two signals at its inputs is conveyed non-inverted, in a subsequent third clock interval both signasl at its inputs are conveyed inverted and in a subsequent fourth clock interval said other of the two signals at its inputs that was not conveyed inverted in the second clock interval is conveyed inverted, and in the second and fourth clock intervals the signals at its inputs are conveyed interchanged in addition to the described inversions.

Claim 17

An arrangement as claimed in claim 15, wherein the period of duration of a clock interval corresponds to the length of a bit interval of said binary data signal.

Claim 18

An arrangement as claimed in calim 16, wherein the preprocessing means comprises a first inverter whose input is connected to a first of the outputs of the baseband converter means, and a second inverter whose input is connected to a second of the outputs of the baseband converter means such that the first and second of the outputs of the baseband converter means and the outputs of the first and second inverters comprise a set of four outputs, a modulo-4 counter, first and second multiplexers each having its own output and its own series of four inputs connected to said set of four outputs, the order of connection of said set of four outputs to the series of four inputs of said first multiplexer being different from the order of connection of said set of four outputs to the series of four inputs of the second multiplexer, said series of four inputs of the respective first and second multiplexers being sequentially connected to the output of the respective first and second multiplexer in accordance with a sequence of states of the modulo-4 counter, the outputs of the first and second multiplexers being connected to the inputs of the equalizer/detector means.

Claim 19

An arrangement as claimed in claim 2, wherein the preprocessing means comprises a first inverter whose input is connected to a first of the outputs of the baseband converter means, and a second inverter whose input is connected to a second of the outputs of the baseband converter means such that the first and second of the outputs of the baseband converter means and the outputs of the first and second inverters comprises a set of four outputs, a modulo-4 counter, first and second multiplexers each having its own output and its own series of four inputs connected to said set of four outputs, the order of connection of said set of four outputs to the series of four inputs of said first multiplexer being different from the order of connection of said set of four outputs to the series of four inputs of the second multiplexer, said series of four inputs of the respective first and second multiplexers being sequentially connected to the output of the respective first and second multiplexer in accordance with a sequence of states of the modulo-4 counter, the outputs of the first and second multiplexers being connected to the inputs of the equalizer/detector means.

Claim 20

An arrangement as claimed in claim 3, wherein the preprocessing means comprises a first inverter whose input is connected to a first of the outputs of the baseband converter means, and a second inverter whose input is connected to a second of the ouputs of the baseband coverter means such that the first and second of the outputs of the baseband coverter means and the outputs of the first and second inverters comprise a set of four outputs, a modulo-4 counter, first and second multiplexers each haivng its own output and its own series of four inputs connected to said set of four outputs, the order of connection of said set of four outputs to the series of four inputs of said first multiplexer being different from the order of connection of said set of four outputs to the series of four inputs of the second multiplexer, said series of four inputs of the respective first and second multiplexers being sequentially connected to the output of the respective first and second multiplexer in accordance with a sequence of states of the modulo-4 counter, the outputs of the first and second multiplexers being connected to the inputs of the equalizer/detector means.

Claim 21

An arrangement as claimed in claim 4, wherein the preprocessing means comprises a first inverter whose input is connected to a first of the outputs of the baseband converter means, and a second inverter whose input is connected to a second of the outputs of the baseband converter means such that the first and second of the outputs of the baseband converter means and the outputs of the first and second inverters comprise a set of four outputs, a modulo-4 counter, first and second multiplexers each having its own output and its own series of four inputs connected to said set of four outputs, the order of connection of said set of four outputs to the series of four inputs of said first multiplexer being different from the order of connection of said set of four outputs to the series of four inputs of the second multiplexer, said series of four inputs of the respective first and second multiplexers being sequentially connected to the output of the respective first and second multiplexer in accordance with a sequence of states of the modulo-4 counter, the outputs of the first and second multiplexers being connected to the inputs of the equalizer/detector means.