US5012127A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronizer circuit with asynchronous clearing
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 1987-09-24
•
Granted: 1991-04-30
•
Expires: 2007-09-24
Abstract
Abstract The present circuit incorporates a latch which latches an asynchronous input signal and provides a latched output signal to the first stage of a two stage synchronizer. An AND gate receives the latched output signal and the output from the first stage such that the output signal from the AND gate follows the output of the first synchronizer and is presented as an input to a second stage of the two stage synchronizer. The second stage is clocked, as is the first stage, with the system clock signal to provide the synchronized output signal. An asynchronous reset of the latch causes the output of the AND gate to go low which in turn causes the output of the second stage to go low asynchronously.
Inventors
- 👤 Dennis E. Gates
- 👤 Bret S. Weber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:38
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/135
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
203 words
A synchronizer circuit with asynchronous clearing comprising: a latch having a data input for receiving an asynchronous input signal that is to be synchronized to a system clock signal and having an output for providing a latched asynchronous input signal, said latch also having a reset input for receiving a clearing signal which resets the output of said latch; a first stage synchronizer having inputs for receiving said latched asynchronous input signal and a system clock signal and an output for providing a system clock synchronized version of said asynchronous input signal; a coincidence gate having one input connected to the output of said latch and another input connected to the output of said first stage synchronizer for providing at its output a signal which is a function of the coincidence of the signals at its inputs; and a second stage synchronizer having inputs for receiving the output signal from said coincidence gate and the system clock signal and an output for providing a second system clock synchronized version of said asynchronous input signal such that receipt of a reset input signal by said latch clears the output from said first and second stage synchronizers upon receipt of the next system clock signal.
Claim 2
Dependent Claim
203 words
A synchronizer circuit with asynchronous clearing comprising: a latch having a data input for receiving an asynchronous input signal that is to be synchronized to a system clock signal and having an output for providing a latched asynchronous input signal, said latch also having a reset input for receiving a clearing signal which resets the output of said latch; a first stage synchronizer having inputs for receiving said latched asynchronous input signal and a system clock signal and an output for providing a system clock synchronized version of said asynchronous input signal; a coincidence gate having one input connected to the output of said latch and another input connected to the output of said first stage synchronizer for providing at its output a signal which is a function of the coincidence of the signals at its inputs; and a second stage synchronizer having inputs for receiving the output signal from said coincidence gate and the system clock signal and an output for providing a second system clock synchronized version of said asynchronous input signal such that receipt of a reset input signal by said latch clears the output from said first and second stage synchronizers upon receipt of the next system clock signal.
Claim 3
Dependent Claim
23 words
A synchronizer circuit with asynchronous clearing according to claim 1 wherein said latch and said first and second stage synchronizers are D-type flip-flops.
Claim 4
Dependent Claim
20 words
A synchronizer circuit with asynchronous clearing according to claim 1 wherein said coincidence gate is a two input AND gate.
Claim 5
Dependent Claim
83 words
A synchronizer circuit with asynchronous clearing comprising: first means for synchronizing the asynchronous occurrence of an input signal to a system clock signal; second means for double synchronizing the output signal from said first means to the system clock signal; and gating means interposed between said first and said second means and responsive to the occurrence of an asynchronous reset signal for clearing said second means; wherein said reset signal clears said first and second means upon receipt of the next clock signal.
Claim 6
Dependent Claim
83 words
A synchronizer circuit with asynchronous clearing comprising: first means for synchronizing the asynchronous occurrence of an input signal to a system clock signal; second means for double synchronizing the output signal from said first means to the system clock signal; and gating means interposed between said first and said second means and responsive to the occurrence of an asynchronous reset signal for clearing said second means; wherein said reset signal clears said first and second means upon receipt of the next clock signal.
Claim 7
Dependent Claim
134 words
A synchronizer circuit with asynchronous clearing comprising: holding means for temporarily holding the state of a two state asynchronous input signal; first synchronizer means for synchronizing the held state of said two state asynchronous input signal to a system clock signal; a second synchronizer means for synchronizing the synchronized output from said first synchronizer means to the system clock signal; and a coincidence gate interposed between the input of said second synchronizer means and the outputs of said holding means and said first synchronizer means such that an asynchronous reset signal applied to said holding means causes said holding means to output a signal having a state other than the one previously held so as to effectively clear the output of said first and second synchronizer means upon receipt of the next clock signal.
Claim 8
Dependent Claim
134 words
A synchronizer circuit with asynchronous clearing comprising: holding means for temporarily holding the state of a two state asynchronous input signal; first synchronizer means for synchronizing the held state of said two state asynchronous input signal to a system clock signal; a second synchronizer means for synchronizing the synchronized output from said first synchronizer means to the system clock signal; and a coincidence gate interposed between the input of said second synchronizer means and the outputs of said holding means and said first synchronizer means such that an asynchronous reset signal applied to said holding means causes said holding means to output a signal having a state other than the one previously held so as to effectively clear the output of said first and second synchronizer means upon receipt of the next clock signal.
Claim 9
Dependent Claim
21 words
A synchronizer circuit with asynchronous clearing according to claim 5 wherein said first and said second synchronizer means are D-type flip-flops.
Claim 10
Dependent Claim
20 words
A synchronizer circuit with asynchronous clearing according to claim 6 wherein said coincidence gate is a two input AND gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-29 | 1994-10-29 | 1995-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-29 | 1998-10-29 | 1999-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-29 | 2002-10-29 | 2003-04-30 | $7700.00 | Window Closed / Lapsed |