Abstract A video signal compression apparatus in which a video signal having a non-matrix pixel arrangement is separated into a plurality of partial images each having a matrix pixel arrangement. The partial images thus separated are interpolated into those containing low-frequency components and those having high-frequency components. The partial images having low-frequency components are coded by an orthogonal transformation while those having high-frequency components are coded by a non-linear quantization or orthogonal transformation. The amount of data is adaptively assigned from the code length of the partial images having high-frequency components to those having low-frequency components, thus effectively utilizing the orthogonal transormation coding which has a great compression effect on a video signal having a non-matrix pixel arrangement. Further, by virtue of a comparatively small amount of data for the signal of high frequency region, the signal of low frequency region having a comparatively great amount of information can be assigned with a greater amount of data thereby to improve the compression efficiency.
Inventors
👤 Masakazu Nishino
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-10-26 05:17
CPC Classifications
H; H04; H04N; H04N19/00; H04N19/60; H04N19/30
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
180 words
A video signal compression apparatus comprising: a separation circuit for receiving a video signal having a non-matrix pixel arrangement and separating the received signal into a plurality of partial images each having a matrix pixel arrangement; an interpolation circuit for producing from a predetermined partial image of the plurality of partial images an interpolated partial image for pixel positions of a remaining partial image of them; a subtractor circuit for producing a differential partial image from the difference between the remaining partial image and the interpolated partial image; an orthogonal transformation and coding circuit for converting the predetermined partial image into a plurality of blocks and coding them by an orthogonal transformation; a coding circuit for converting the differential partial image into plural blocks to code them; a code length estimate circuit for determining a code length of a coded output of the coding circuit; and a code length assignment circuit for assigning a code length of a coded output of the orthogonal transformation and coding circuit adaptively by a code length output determined by the code length estimate circuit.
Claim 2
Dependent Claim
180 words
A video signal compression apparatus comprising: a separation circuit for receiving a video signal having a non-matrix pixel arrangement and separating the received signal into a plurality of partial images each having a matrix pixel arrangement; an interpolation circuit for producing from a predetermined partial image of the plurality of partial images an interpolated partial image for pixel positions of a remaining partial image of them; a subtractor circuit for producing a differential partial image from the difference between the remaining partial image and the interpolated partial image; an orthogonal transformation and coding circuit for converting the predetermined partial image into a plurality of blocks and coding them by an orthogonal transformation; a coding circuit for converting the differential partial image into plural blocks to code them; a code length estimate circuit for determining a code length of a coded output of the coding circuit; and a code length assignment circuit for assigning a code length of a coded output of the orthogonal transformation and coding circuit adaptively by a code length output determined by the code length estimate circuit.
Claim 3
Dependent Claim
27 words
An apparatus according to claim 1, wherein the coding circuit converts the differential partial image into a plurality of blocks and codes them by an orthogonal transformation.
Claim 4
Dependent Claim
27 words
An apparatus according to claim 1, wherein the coding circuit separates the differential partial image into a plurality of blocks and codes them by a non-linear quantization.
Claim 5
Dependent Claim
223 words
A video signal compression apparatus comprising: a separation circuit for receiving a video signal having a non-matrix pixel arrangement to separate the received signal into a plurality of partial images having a matrix pixel arrangement; a first interpolation circuit for producing from a predetermined one of the partial images a first interpolated partial image for pixel positions of a remaining partial image; a second interpolation circuit for producing from the remaining partial image a second interpolated partial image for pixel positions of the predetermined partial image; a subtractor circuit for producing a differential partial image from the difference between the remaining partial image and the first interpolated partial image; an adder circuit for producing a sum partial image by adding the predetermined partial image to the second interpolated partial image; an orthogonal transformation and coding circuit for converting the sum partial image into a plurality of blocks to code them by an orthogonal transformation; a coding circuit for converting the differential partial image into a plurality of blocks to code them; a code length estimate circuit for determining a code length of a coded output of the coding circuit; and a code length assignment circuit for assigning a code length of a coded output of the orthogonal transformation and coding circuit adaptively by the code length determined by the code length estiamte circuit.
Claim 6
Dependent Claim
223 words
A video signal compression apparatus comprising: a separation circuit for receiving a video signal having a non-matrix pixel arrangement to separate the received signal into a plurality of partial images having a matrix pixel arrangement; a first interpolation circuit for producing from a predetermined one of the partial images a first interpolated partial image for pixel positions of a remaining partial image; a second interpolation circuit for producing from the remaining partial image a second interpolated partial image for pixel positions of the predetermined partial image; a subtractor circuit for producing a differential partial image from the difference between the remaining partial image and the first interpolated partial image; an adder circuit for producing a sum partial image by adding the predetermined partial image to the second interpolated partial image; an orthogonal transformation and coding circuit for converting the sum partial image into a plurality of blocks to code them by an orthogonal transformation; a coding circuit for converting the differential partial image into a plurality of blocks to code them; a code length estimate circuit for determining a code length of a coded output of the coding circuit; and a code length assignment circuit for assigning a code length of a coded output of the orthogonal transformation and coding circuit adaptively by the code length determined by the code length estiamte circuit.
Claim 7
Dependent Claim
27 words
An apparatus according to claim 4, wherein the coding circuit converts the differential partial image into a plurality of blocks to code them by an orthogonal transformation.
Claim 8
Dependent Claim
27 words
An apparatus according to claim 4, wherein the coding circuit converts the differential partial image into a plurality of blocks to code them by a non-linear quantization.