US5007005A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processing system
Assignee: Hitachi Ltd
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Filing: 1989-03-28
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Granted: 1991-04-09
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Expires: 2009-03-28
Abstract
Abstract A data processing system capable of implementing at high speeds animating image generation processing and animating image display processing in synchronization with each other, thereby generating and displaying an animating image in a real time. The data processing system uses a given memory area of a storage unit as a screen buffer memory for storing an animating image data for each screen and is provided with an image processor for writing an animating image data for each screen in a screen buffer memory, an image display processor for reading the animating image data for from the screen buffer memory and for generating a display screen graphic signal to be supplied to a display unit and a hardware register circuit having a screen read-out control register corresponding to the animating image data for each screen of the screen buffer memory. The hardware register circuit updates data of the screen read-out control register in synchronization with each of a write operation of an animating image data from the image processor and a read operation of the animating image data to the image display processor. A delivery and a receipt of the data of the animating image data for each screen is carried out at high speeds between the image processor and the image display processor through the screen buffer memory storing the animating image data therefor by a control of the hardware register circuit.
Inventors
- 👤 Yasuhiko Hatakeyama
- 👤 Tomoo Aoyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 03:46
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/363; G09G5/39; G09G5/399
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
103 words
A data processing system comprising: an image processor for generating animating image data for each of a plurality of screens and writing said animating image data in a screen buffer memory; an image display processor for reading said animating image data from said screen buffer memory and generating a display screen graphic signal to be supplied to a display unit; and a hardware register circuit for updating data of a screen read-out control register in synchronization with each of a write operation of animating image data from said image processor and a read operation of animating image data to said image display processor.
Claim 2
Dependent Claim
103 words
A data processing system comprising: an image processor for generating animating image data for each of a plurality of screens and writing said animating image data in a screen buffer memory; an image display processor for reading said animating image data from said screen buffer memory and generating a display screen graphic signal to be supplied to a display unit; and a hardware register circuit for updating data of a screen read-out control register in synchronization with each of a write operation of animating image data from said image processor and a read operation of animating image data to said image display processor.
Claim 3
Dependent Claim
77 words
A data processing system as claimed in claim 1, wherein said hardware register circuit is provided with a screen read-out control register corresponding to animating image data for each screen in the screen buffer memory and said hardware register circuit updates data of said screen read-out control register in synchronization with each of said write operation of animating image data from said image processor and said read operation of animating image data to said image display processor.
Claim 4
Dependent Claim
32 words
A data processing system as claimed in claim 1, wherein a predetermined memory area of a storage unit functions as said screen buffer memory for storing animating image data for each screen.
Claim 5
Dependent Claim
143 words
A data processing system comprising: an image processor for generating animating image data for each of a plurality of screens and writing said animating image data in a screen buffer memory which uses a predetermined memory area of a storage unit for storing said animating image data; an image display processor for reading said animating image data from said screen buffer memory and generating a display screen graphic signal to be supplied to a display unit; and a hardware register circuit having a screen read-out control register corresponding to said animating image data for each screen in said screen buffer memory, said hardware register circuit updates data of said screen read-out control register in synchronization with each of a write operation of animating image data from said image processor and a read operation of said animating image data to said image display processor.
Claim 6
Dependent Claim
143 words
A data processing system comprising: an image processor for generating animating image data for each of a plurality of screens and writing said animating image data in a screen buffer memory which uses a predetermined memory area of a storage unit for storing said animating image data; an image display processor for reading said animating image data from said screen buffer memory and generating a display screen graphic signal to be supplied to a display unit; and a hardware register circuit having a screen read-out control register corresponding to said animating image data for each screen in said screen buffer memory, said hardware register circuit updates data of said screen read-out control register in synchronization with each of a write operation of animating image data from said image processor and a read operation of said animating image data to said image display processor.
Claim 7
Dependent Claim
55 words
A data processing system as claimed in claims 1 or 4, wherein said screen buffer memory storing said animating image data is provided in a predetermined memory area of a main storage unit and said animating image data generated by said image processor is written in said screen buffer memory of said main storage unit.
Claim 8
Dependent Claim
55 words
A data processing system as claimed in claims 1 or 4, wherein said screen buffer memory storing said animating image data is provided in a predetermined memory area of an extended storage unit and said animating image data generated by the image processor is written in said screen buffer memory of said extended storage unit.
Claim 9
Dependent Claim
58 words
A data processing system as claimed in claims 1 or 4, wherein said image display processor is provided with a digital/analog converter and a low path filter and said animating image data written in said screen buffer memory is read from said screen buffer memory, said digital/analog converter generates said display screen graphic signal as an analog signal.
Claim 10
Dependent Claim
93 words
A data processing system as claimed in claims 1 or 4, wherein said hardware register circuit is provided with a screen read-out control register corresponding to said animating image data for each screen in said screen buffer memory, said hardware register circuit updates data of said screen read-out control register in synchronization with each of said write operation of said image processor for writing said animating image data in said screen buffer memory or said read operation of said image display processor for reading said animating image data from said screen buffer memory.
Claim 11
Dependent Claim
104 words
A data processing method for a data processing system having a screen buffer memory, an image processor, an image display processor, and a hardware register circuit, comprising the steps of: processing an image by said image processor including the substeps of generating an image, writing said image in said screen buffer memory, and updating data of a screen read-out control register of said hardware register circuit; and processing a display of said image by said image display processor including the substeps of reading said image from said screen buffer memory and updating data of said screen read-out control register of said hardware register circuit.
Claim 12
Dependent Claim
104 words
A data processing method for a data processing system having a screen buffer memory, an image processor, an image display processor, and a hardware register circuit, comprising the steps of: processing an image by said image processor including the substeps of generating an image, writing said image in said screen buffer memory, and updating data of a screen read-out control register of said hardware register circuit; and processing a display of said image by said image display processor including the substeps of reading said image from said screen buffer memory and updating data of said screen read-out control register of said hardware register circuit.
References Cited (Backward Citations)
US4864289A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-08 | 1994-10-08 | 1995-04-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-08 | 1998-10-08 | 1999-04-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-08 | 2002-10-08 | 2003-04-09 | $7700.00 | Window Closed / Lapsed |