US5004983A
Expired / Lapsed
US
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Circuit arrangement for generating rf signals for MR examinations
Assignee: US Philips Corp
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Filing: 1989-06-01
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Granted: 1991-04-02
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Expires: 2009-06-01
Abstract
Abstract The invention relates to a circuit arrangement for generating rf signals for MR examinations, comprising a read-only memory in which a signal is stored in the form of a series of data words, an address generator for reading data words from the read-only memory with a clock frequency, and a digital-to-analog converter which succeeds the read-only memory. In order to reduce the required storage capacity, a sinusoidal signal in the form of a series of data words is stored in the memory.
Inventors
- 👤 Roland Proksa
- 👤 Peter Roschmann
- 👤 Noel J. M. Van Den Berg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 13:29
CPC Classifications
G; G01; G01R; G01R33/00; G01R33/20; G01R33/28; G01R33/32; G01R33/36; G01R33/3607
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
152 words
A circuit arrangement for generating rf signals at a Larmor frequency "f L " for transmission into an examination zone during MR examinations, comprising a read-only memory in which samples of a sinusoidal waveform are stored in the form of a series of data words, an address generator means for reading data words from the read-only memory with a clock frequency "f T " such that cycles of the sinusoidal waveform are read out from said read-only memory with a frequency "f S ", there being at least two data words read from the read-only memory for each cycle of the sinusoidal waveform, and a digital-to-analog converter which succeeds the read-only memory, wherein "f T " and "f S " are chosen such that a frequency spectrum at the output of the digital-to-analog converter comprises a spectral line at the Larmor frequency f L , and wherein f L >f S .
Claim 2
Dependent Claim
152 words
A circuit arrangement for generating rf signals at a Larmor frequency "f L " for transmission into an examination zone during MR examinations, comprising a read-only memory in which samples of a sinusoidal waveform are stored in the form of a series of data words, an address generator means for reading data words from the read-only memory with a clock frequency "f T " such that cycles of the sinusoidal waveform are read out from said read-only memory with a frequency "f S ", there being at least two data words read from the read-only memory for each cycle of the sinusoidal waveform, and a digital-to-analog converter which succeeds the read-only memory, wherein "f T " and "f S " are chosen such that a frequency spectrum at the output of the digital-to-analog converter comprises a spectral line at the Larmor frequency f L , and wherein f L >f S .
Claim 3
Dependent Claim
56 words
A circuit arrangement as claimed in claim 1, wherein the clock frequency "f T " and the frequency "f S " of reading cycles of the sinusoidal waveform from the read-only memory are chosen so that: f.sub.L =nf.sub.T +af.sub.S where "n" is a positive integer larger than zero, and "a" has the value +1 or -1.
Claim 4
Dependent Claim
76 words
A circuit arrangement as claimed in claim 1, characterized in that the address generator comprises a counting device whose counting position can be changed by a presettable amount with the clock frequency, the counting capacity of the counting device being a multiple of the number of addressable memory locations in the read-only memory, an address signal for the read-only memory being derived from an bits of a part of the output signal of the counting device.
Claim 5
Dependent Claim
64 words
A circuit arrangement as claimed in claim 1, characterized in that the address generator comprises a counting device (101, 102) whose counting position can be varied by a presettable amount with the clock frequency, between the counting device and the read-only memory (11) there being connected a multiplier circuit (103) in which the counting position is each time multiplied by a presettable factor (f(t)).
Claim 6
Dependent Claim
43 words
A circuit arrangement as claimed in claim 1, characterized in that between the read-only memory (11) and the digital-to-analog converter (14) there is connected a multiplier circuit (12) which multiplies the data words read from the read-only memory by a presettable factor (a(t)).
Claim 7
Dependent Claim
25 words
A circuit arrangement as claimed in claim 1, characterized in that a last stage of the address generator is formed by an adder circuit (105).
Claim 8
Dependent Claim
47 words
A circuit arrangement as claimed in claim 3, characterized in that the counting device comprises an adding circuit (101) whose output is connected, via a memory (102), to one input of the adding circuit, a constant value being present on a second input of the adding circuit.
Claim 9
Dependent Claim
76 words
A circuit arrangement as claimed in claim 2, characterized in that the address generator comprises a counting device whose counting position can be changed by a presettable amount with the clock frequency, the counting capacity of the counting device being a multiple of the number of addressable memory locations in the read-only memory, an address signal for the read-only memory being derived from the bits of a part of an output signal of the counting device.
Claim 10
Dependent Claim
64 words
A circuit arrangement as claimed in claim 2, characterized in that the address generator comprises a counting device (101, 102) whose counting position can be varied by a presettable amount with the clock frequency, between the counting device and the read-only memory (11) there being connected a multiplier circuit (103) in which the counting position is each time multiplied by a presettable factor (f(t)).
Claim 11
Dependent Claim
64 words
A circuit arrangement as claimed in claim 8, characterized in that the address generator comprises a counting device (101, 102) whose counting position can be varied by a presettable amount with the clock frequency, between the counting device and the read-only memory (11) there being connected a multiplier circuit (103) in which the counting position is each time multiplied by a presettable factor (f(t)).
Claim 12
Dependent Claim
43 words
A circuit arrangement as claimed in claim 2, characterized in that between the read-only memory (11) and the digital-to-analog converter (14) there is connected a multiplier circuit (12) which multiplies the data words read from the read-only memory by a presettable factor (a(t)).
Claim 13
Dependent Claim
43 words
A circuit arrangement as claimed in claim 3, characterized in that between the read-only memory (11) and the digital-to-analog converter (14) there is connected a multiplier circuit (12) which multiplies the data words read from the read-only memory by a presettable factor (a(t)).
Claim 14
Dependent Claim
43 words
A circuit arrangement as claimed in claim 4, characterized in that between the read-only memory (11) and the digital-to-analog converter (14) there is connected a multiplier circuit (12) which multiplies the data words read from the read-only memory by a presettable factor (a(t)).
Claim 15
Dependent Claim
43 words
A circuit arrangement as claimed in claim 10, characterized in that between the read-only memory (11) and the digital-to-analog converter (14) there is connected a multiplier circuit (12) which multiplies the data words read from the read-only memory by a presettable factor (a(t)).
Claim 16
Dependent Claim
25 words
A circuit arrangement as claimed in claim 2, characterized in that a last stage of the address generator is formed by an adder circuit (105).
Claim 17
Dependent Claim
25 words
A circuit arrangement as claimed in claim 3, characterized in that a last stage of the address generator is formed by an adder circuit (105).
Claim 18
Dependent Claim
25 words
A circuit arrangement as claimed in claim 4, characterized in that a last stage of the address generator is formed by an adder circuit (105).
Claim 19
Dependent Claim
25 words
A circuit arrangement as claimed in claim 14, characterized in that a last stage of the address generator is formed by an adder circuit (105).
Claim 20
Dependent Claim
39 words
A circuit arrangement as claimed in claim 4, characterized in that the output is connected, via a memory (102), to one input of the adding circuit, a constant value being present on a second input of the adding circuit.
Claim 21
Dependent Claim
39 words
A circuit arrangement as claimed in claim 18, characterized in that the output is connected, via a memory (102), to one input of the adding circuit, a constant value being present on a second input of the adding circuit.
References Cited (Backward Citations)
US4054785A
Cited
US4613814A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-01 | 1994-10-01 | 1995-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-01 | 1998-10-01 | 1999-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-01 | 2002-10-01 | 2003-04-02 | $7700.00 | Window Closed / Lapsed |