Computer game cartridge security circuit

Claim 3

The method according to claim 1 wherein the step of generating a sequence of pulses includes the steps of: generating the first pulse of the sequence of pulses to have a fixed duration, and generating the pulses after the first pulse to occur pseudo-randomly.

Claim 4

For a computer system having a security circuit that disables operation of the system for a time upon its initialization and then cycles it between being enabled and disabled by a periodically varying reset signal until a proper authentication signal is communicated to the system, a removable memory device comprising: a computer memory containing a stored software program that is electrically connectable to said computer system, means connectable to said computer system for reconstructing the periodically varying reset signal, whereby said reconstructed reset signal begins in a disabled state for a time after initialization and then switches to an enabled state, means connected to said reconstructing means and responsive to the reconstructed reset signal for generating a security signal characterized by being inactive while said reconstructed reset signal is in the disabled state and active while the reconstructed reset signal is in the enable state, said security signal changing from its said inactive state to its said active state substantially coincident with the reconstructed reset signal changing from its disabled state to its enabled state, and means for connecting the security signal with the security circuit of the computer system.

Claim 5

For a computer system having a security circuit that disables operation of the system for a time upon its initialization and then cycles it between being enabled and disabled by a periodically varying reset signal until a proper authentication signal is communicated to the system, a removable memory device comprising: a computer memory containing a stored software program that is electrically connectable to said computer system, means connectable to said computer system for reconstructing the periodically varying reset signal, whereby said reconstructed reset signal begins in a disabled state for a time after initialization and then switches to an enabled state, means connected to said reconstructing means and responsive to the reconstructed reset signal for generating a security signal characterized by being inactive while said reconstructed reset signal is in the disabled state and active while the reconstructed reset signal is in the enable state, said security signal changing from its said inactive state to its said active state substantially coincident with the reconstructed reset signal changing from its disabled state to its enabled state, and means for connecting the security signal with the security circuit of the computer system.

Claim 6

The computer system removable memory device according to claim 3 wherein said security signal generating means includes means responsive to the reconstructed reset signal for generating a pulse having a leading edge that is substantially coincident with the switching of the reconstructed reset signal from its disabled to enabled state.

Claim 7

The computer system removable memory device according to claim 3 wherein said computer system includes an address bus, and wherein said reset signal reconstructing means includes means connected to said bus and responsive to a least significant bit of the computer system address bus for driving the reconstructed reset signal to its enabled state for a time after a transition of the least significant address bit value.

Claim 8

The computer system removable memory device according to claim 3 wherein the computer system with which it operates includes a videographics console having a plug and said removable memory device is in the form of a plug-in cartridge adapted to fit into said plug.

Claim 9

The computer system removable memory device according to claim 3 wherein said computer memory includes read-only memory (ROM), and further wherein at least a portion of said ROM, said reconstructing means, and said security signal generating means are formed as part of a single integrated circuit chip.

Claim 10

The computer system removable memory device according to claim 3 wherein said security signal connection means includes a series capacitor.

Claim 11

A computer game cartridge, comprising: a case, a first connector part provided along an edge of the case and adapted to mate with a second connector part on a videographics console computer system, thereby electrically interconnecting signals between the cartridge and the console, a computer memory containing a software program housed within said case and electrically connected to said first connector part, means within said case attached to said first connector part and responsive to a first interconnectable signal for generating an activity signal having an active state when the console computer system is active and an inactive state when the console computer system is inactive, and means within said case attached to said activity signal generating means and responsive to said activity signal for generating a second interconnectable signal connected to said first connector part, said second interconnectable signal being in an inactive state when said activity signal is inactive and including a series of pulses when said activity signal is in an active state.

Claim 12

A computer game cartridge, comprising: a case, a first connector part provided along an edge of the case and adapted to mate with a second connector part on a videographics console computer system, thereby electrically interconnecting signals between the cartridge and the console, a computer memory containing a software program housed within said case and electrically connected to said first connector part, means within said case attached to said first connector part and responsive to a first interconnectable signal for generating an activity signal having an active state when the console computer system is active and an inactive state when the console computer system is inactive, and means within said case attached to said activity signal generating means and responsive to said activity signal for generating a second interconnectable signal connected to said first connector part, said second interconnectable signal being in an inactive state when said activity signal is inactive and including a series of pulses when said activity signal is in an active state.

Claim 13

The computer game cartridge according to claim 9 wherein the second interconnectable signal generating means includes means responsive to said activity signal for generating a first pulse of said series of pulses with a leading edge substantially coincident with the activity signal changing from its said inactive state to its said active state.

Claim 14

The computer game cartridge according to claim 9 wherein second interconnectable signal includes a signal generated by a pseudo-random pulse generator.

Claim 15

The computer game cartridge according to claim 9 wherein the memory electrical connections with said first connector part include an address bus, and wherein said first interconnectable signal originates from said address bus.

Claim 16

An electronic system, comprising on a single intergrated circuit chip: a computer memory having a plurality of address and data bus connections, means attached to at least one of said bus connections and responsive to signals received on said bus connections for generating an activity signal having an active state when there is signal activity on said bus and an inactive state when there is no signal activity on said bus, and means connected to said activity signal generating means and responsive to said activity signal for generating a security signal at another connection, said security signal being in an inactive state when said activity signal is inactive and including a series of pulses when said activity signal is in an active state.

Claim 17

An electronic system, comprising on a single intergrated circuit chip: a computer memory having a plurality of address and data bus connections, means attached to at least one of said bus connections and responsive to signals received on said bus connections for generating an activity signal having an active state when there is signal activity on said bus and an inactive state when there is no signal activity on said bus, and means connected to said activity signal generating means and responsive to said activity signal for generating a security signal at another connection, said security signal being in an inactive state when said activity signal is inactive and including a series of pulses when said activity signal is in an active state.

Claim 20

The method according to claim 14 wherein the step of generating a sequence of pulses includes the steps of: generating the first pulse of the sequence of pulses to have a fixed duration, and generating the pulses after the first pulse to occur pseudo-randomly.

Claim 21

For a computer game system having a security circuit that disables operation of the system for a time upon its initialization and then cycles it between enabled and disabled states until a proper authentication signal is communicated to the system, a removable memory device comprising: a computer memory containing a stored game software program that is electrically connectable to said computer system, means connectable to said computer system for identifying when the computer system is in its said enabled state and when it is in its said disabled state, whereby the disabled state is identified for a time after initialization until the computer system is known to switch to the enabled state, means connected to said identifying means for generating a security signal characterized by being inactive while said computer system is known to be in the disabled state and active while the computer system is known to be in the enable state, said security signal changing from its said inactive state to its said active state substantially coincident with the computer system being switched to an enabled state, and means responsive to said generating means for connecting the security signal with the security circuit of the computer system as said proper authentication signal.

Claim 22

For a computer game system having a security circuit that disables operation of the system for a time upon its initialization and then cycles it between enabled and disabled states until a proper authentication signal is communicated to the system, a removable memory device comprising: a computer memory containing a stored game software program that is electrically connectable to said computer system, means connectable to said computer system for identifying when the computer system is in its said enabled state and when it is in its said disabled state, whereby the disabled state is identified for a time after initialization until the computer system is known to switch to the enabled state, means connected to said identifying means for generating a security signal characterized by being inactive while said computer system is known to be in the disabled state and active while the computer system is known to be in the enable state, said security signal changing from its said inactive state to its said active state substantially coincident with the computer system being switched to an enabled state, and means responsive to said generating means for connecting the security signal with the security circuit of the computer system as said proper authentication signal.

Claim 23

The computer system removable memory device according to claim 16 wherein said security signal generating means includes means for generating a pulse having a leading edge that is substantially coincident with the switching of the computer system from its said disabled to its said enabled state.

Claim 24

The computer system removable memory device according to claim 16 wherein said computer memory includes read-only-memory (ROM), and further wherein at least a portion of said ROM, said detecting means, and said security signal generating means are formed as part of a single integrated circuit chip.