Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
208 words
A speech recognition LSI comprising: a plurality of band-pass filters for dividing a speech input signal into a plurality of different frequency bands; rectifier circuits for rectifying outputs of said band-pass filters; low-pass filters for smoothing outputs of said rectifier circuit, each having a cut-off frequency; A/D converter means for A/D converting outputs of said low-pass filter; first sampling means for sampling an output of said A/D converter means at a first frame interval; digital low-pass filter means for storing and smoothing a plurality of frames of data samples by said first sampling means; second sampling means for sampling an output of said digital low-pass filter means at a second frame interval, longer than the first frame interval, the first frame interval in the first sampling means being shorter than 1/2fc when the cut-off frequency of the low-pass filters is fc, and the second frame interval in the second sampling means being longer than 1/2fc; and recognition-processing means for detecting the speech segment of data time-sequentially supplied from said second sampling means, checking the matching as regards the data in each speech segment and reference pattern data, to detect similarities therebetween, and recognizing the data in each speech segment, on the basis of magnitude of the similarities detected.
Claim 2
Dependent Claim
208 words
A speech recognition LSI comprising: a plurality of band-pass filters for dividing a speech input signal into a plurality of different frequency bands; rectifier circuits for rectifying outputs of said band-pass filters; low-pass filters for smoothing outputs of said rectifier circuit, each having a cut-off frequency; A/D converter means for A/D converting outputs of said low-pass filter; first sampling means for sampling an output of said A/D converter means at a first frame interval; digital low-pass filter means for storing and smoothing a plurality of frames of data samples by said first sampling means; second sampling means for sampling an output of said digital low-pass filter means at a second frame interval, longer than the first frame interval, the first frame interval in the first sampling means being shorter than 1/2fc when the cut-off frequency of the low-pass filters is fc, and the second frame interval in the second sampling means being longer than 1/2fc; and recognition-processing means for detecting the speech segment of data time-sequentially supplied from said second sampling means, checking the matching as regards the data in each speech segment and reference pattern data, to detect similarities therebetween, and recognizing the data in each speech segment, on the basis of magnitude of the similarities detected.
Claim 3
Dependent Claim
50 words
A speech recognition LSI system according to claim 1, wherein said A/D converter means includes a switching circuit for selecting one of the output signals of said low-pass filters and an A/D converter for A/D converting one from among output signals of said low-pass filters selected by said switching circuit.
Claim 4
Dependent Claim
57 words
A speech recognition LSI system according to claim 1, wherein said A/D converter means includes a plurality of A/D converters to which are supplied output signals of said low-pass filters; and said A/D output processing means includes a plurality of A/D output processing sections to which are respectively supplied output signals of said plurality of A/D converters.
Claim 5
Dependent Claim
30 words
A speech recognition LSI system according to claim 1, wherein said digital low-pass filter means is attained by means of an MPU which is operated according to a predetermined program.
Claim 6
Dependent Claim
67 words
A speech recognition LSI system according to claim 1, wherein said digital low-pass filter means includes delay means having a delay time equal to the first frame interval in said first sampling means, multiplier means for multiplying an output signal of said first sampling means and delay outputs of said delay means by preset coefficients, and adding means for adding together output signals of said multiplier means.
Claim 7
Dependent Claim
118 words
A speech recognition LSI system according to claim 1, wherein said recognition-processing means includes a speech segment detecting section for detecting the speech segment of data time-sequentially supplied from said A/D output processing section, a data memory section for temporarily storing data in the speech segment detected by said speech segment detecting section, a reference pattern memory section which stores reference pattern data used for speech recognition, a matching section for detecting the degree of matching as regards data stored in said data memory section and said reference pattern memory section, and a recognition-determination section for deriving the recognition result on the basis of the magnitude of similarity detected in the matching-checking operation performed by said matching section.
Claim 8
Dependent Claim
118 words
A speech recognition LSI system according to claim 1, wherein said recognition-processing means includes a data memory section for storing data time-sequentially supplied from said A/D output processing section, a speech segment detecting section for detecting the speech segment of the time-sequential data stored in said data memory section, a reference pattern memory section which stores reference pattern data used for speech recognition, a matching section for detecting the degree of matching as regards an output of said speech segment detecting section and data stored in said reference pattern memory section, and a recognition-determination section for deriving the recognition result, on the basis of the magnitude of similarity detected in the matching-checking operation performed by said matching section.