Neural network using random binary code

Claim 1

A method of analog, parallel hardware implementation of neural networks with changeable connectivity pattern and changeable long term memory traces comprising: arranging a plurality of processors into a two dimensional array comprising: linear arrays of processors; pipeline buses common to one or more of said linear arrays; means for access of input signals; means for retrieval of output signals; means for access of control signals to each processor; arranging said processors of said linear arrays to absorb and to emit energy in the form of modulated energy emissions from and into one or more pipeline buses common to at least a part of said linear arrays, binary modulation of energy emissions depending on analog characteristics of absorbed energy; arranging advantageous delay and duration of activation of a random code generator, said binary modulation being a function of a random output from the random code generator; using averages of the binary codes of said processors' energy emissions as short term memory traces of a neural network; using the ratios of second correlations of pairs of codes to the products of their averages as long term memory traces of a neural network.

Claim 2

A method of analog, parallel hardware implementation of neural networks with changeable connectivity pattern and changeable long term memory traces comprising: arranging a plurality of processors into a two dimensional array comprising: linear arrays of processors; pipeline buses common to one or more of said linear arrays; means for access of input signals; means for retrieval of output signals; means for access of control signals to each processor; arranging said processors of said linear arrays to absorb and to emit energy in the form of modulated energy emissions from and into one or more pipeline buses common to at least a part of said linear arrays, binary modulation of energy emissions depending on analog characteristics of absorbed energy; arranging advantageous delay and duration of activation of a random code generator, said binary modulation being a function of a random output from the random code generator; using averages of the binary codes of said processors' energy emissions as short term memory traces of a neural network; using the ratios of second correlations of pairs of codes to the products of their averages as long term memory traces of a neural network.

Claim 5

A method of implementing a neural network comprising: interconnecting a plurality of processors to detect and emit energy from and to at least one bus; and during code times modulating the energy detection and emission relative to each processor as a function of a random binary code and controlling the timing of said code times during which the energy is detected and emitted, wherein the timing includes the time delay t d of a code time T c , during which random binary code is activated, within a pulse time T p during which a code time may occur.

Claim 6

A method of implementing a neural network comprising: interconnecting a plurality of processors to detect and emit energy from and to at least one bus; and during code times modulating the energy detection and emission relative to each processor as a function of a random binary code and controlling the timing of said code times during which the energy is detected and emitted, wherein the timing includes the time delay t d of a code time T c , during which random binary code is activated, within a pulse time T p during which a code time may occur.