US4995092A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for white level acquisition for the black/white quantization of the scan signals of individual photo sensors
Assignee: Oce Document Technologies GmbH
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Filing: 1989-09-25
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Granted: 1991-02-19
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Expires: 2009-09-25
Abstract
Abstract A circuit arrangement is composed of a first adder whose first output is assigned to the digitized output signals of the photosensors and a second input connected to the outputs of a white level memory, and a second adder at whose input side the currently stored white level are linked with the correction signal and which reads the resultant signal back into the white level memory, the comparator following the first adder which, dependent upon the threshold level derived from maximum and average blackening values of the output signal of the first adder supplies a black signal or a white signal. A correction signal derived from a plurality of influencing variables serves for white level correction, the correction signal supplying a white level increment/decrement for delivery into the white level memory dependent on a carry signal that appears or, respectively, that does not appear at the first adder.
Inventors
- 👤 Wilfried Kochert
- 👤 Dietmar Dowe
- 👤 Hans-Joachim Schwarz
- 👤 Eberhard Ullrich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 09:51
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/40; H04N1/403; G; G06; G06V; G06V10/00; G06V10/20; G06V10/28
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
178 words
A circuit arrangement for white level acquisition for the black/white quantization of the scan signals of individual photosensors having different gray levels, comprising: a first adder including a first input for receiving digitized output signals of the photosensors, a second input, a first output and a second output; a white level memory connected to said second input of said first adder; a second adder including a first input connected to said white level memory, a second input, a first output and a second output; a comparator connected to said first adder and supplying a black signal or a white signal dependent on a threshold value derived from maximum blackening values and average blackening values from said first adder; and said second output of said first adder connected to said second adder to cause said second adder to provide a variable correction signal derived from a plurality of influencing variables dependent on a carry signal appearing at said second output of said first adder such that said second adder provides a white level increment/decrement to said white level memory.
Claim 2
Dependent Claim
178 words
A circuit arrangement for white level acquisition for the black/white quantization of the scan signals of individual photosensors having different gray levels, comprising: a first adder including a first input for receiving digitized output signals of the photosensors, a second input, a first output and a second output; a white level memory connected to said second input of said first adder; a second adder including a first input connected to said white level memory, a second input, a first output and a second output; a comparator connected to said first adder and supplying a black signal or a white signal dependent on a threshold value derived from maximum blackening values and average blackening values from said first adder; and said second output of said first adder connected to said second adder to cause said second adder to provide a variable correction signal derived from a plurality of influencing variables dependent on a carry signal appearing at said second output of said first adder such that said second adder provides a white level increment/decrement to said white level memory.
Claim 3
Dependent Claim
57 words
The circuit arrangement of claim 1, and further comprising a multiplexer including a first input connected to said first output of said first adder, a second input for receiving all "0" and a third input for receiving a carry signal from the second output of said first adder, said multiplexer including an output connected to said comparator.
Claim 4
Dependent Claim
58 words
The circuit arrangement of claim 1, and further comprising: a driver connected to said second output of said second adder and said driver including an input for receiving all "0" and an output connected to said white level memory for writing "0" bits into said white level memory in response to the carry signal of said second adder.
Claim 5
Dependent Claim
160 words
A circuit arrangement for white level acquisition for the black/white quantization of the scan signals of photosensors having different grey levels, comprising: a first adder including a first input for receiving digitalized output signals of the photosensors, a second input, a first output and a second output; a white level memory connected to said second input of said first adder; a second adder including a first input connected to said white level memory, a second input, a first output and a second output; a comparator connected to said first adder and supplying a black signal or a white signal dependent on a threshold value derived from maximum blackening values and average blackening values from said first adder; said second adder producing a variable correction signal derived from a plurality of influencing variables; and said correction signal providing a white level increment/decrement to said white level memory dependent on a carry signal appearing at said second output of said first adder.
Claim 6
Dependent Claim
160 words
A circuit arrangement for white level acquisition for the black/white quantization of the scan signals of photosensors having different grey levels, comprising: a first adder including a first input for receiving digitalized output signals of the photosensors, a second input, a first output and a second output; a white level memory connected to said second input of said first adder; a second adder including a first input connected to said white level memory, a second input, a first output and a second output; a comparator connected to said first adder and supplying a black signal or a white signal dependent on a threshold value derived from maximum blackening values and average blackening values from said first adder; said second adder producing a variable correction signal derived from a plurality of influencing variables; and said correction signal providing a white level increment/decrement to said white level memory dependent on a carry signal appearing at said second output of said first adder.
Claim 7
Dependent Claim
73 words
The circuit arrangement of claim 4, wherein: said second adder is constructed to produce said correction signal from the most significant bit of a signal at said first output of said first adder and from a pulse derived from the most significant bit of the scan signal and from a control variable bit derived from the two most significant bits of the scan signal referred to a control of a scan light source.
Claim 8
Dependent Claim
61 words
The circuit arrangement of claim 4, and further comprising: an AND gate including first and second inputs respectively connected to receive the first and second most significant bits of the scan signal, and an output; a delay circuit including an input connected to said output of said AND gate, and an output connected to said second input of said second adder.
Claim 9
Dependent Claim
37 words
The circuit arrangement of claim 4, and further comprising: a counter including an input connected to receive the most significant bit of the scan signal, and an output connected to said second input of said second adder.
Claim 10
Dependent Claim
57 words
The circuit arrangement of claim 4, and further comprising: a multiplexer including a first input connected to said first output of said first adder, a second input for receiving all "0'" and a third input for receiving a carry signal from the second output of said first adder, said multiplexer including an output connected to said comparator.
Claim 11
Dependent Claim
55 words
The circuit arrangement of claim 4, and further comprising: a driver connected to said second output of said second adder and an input for receiving all "0'" and an output connected to said white level memory for stepping "0" bits into said white level memory in response to the carry signal of said second adder.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-18 | 1994-08-20 | 1995-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-18 | 1998-08-20 | 1999-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-18 | 2002-08-20 | 2003-02-19 | $7700.00 | Window Closed / Lapsed |