US4992876A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Noise reduction circuit for an imaging and recording apparatus with an MOS solid-state imaging device
Assignee: Hitachi Ltd
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Filing: 1989-07-31
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Granted: 1991-02-12
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Expires: 2009-07-31
Abstract
Abstract A noise reduction circuit receives a periodic signal from an imaging device, and includes first and second circuits in which noise components opposite in phase are offset by delaying the input signal to produce a delayed signal and adding the delayed signal and the input signal. The output of the first circuit is supplied to a low pass filter, while the output of the second circuit is integrated through a first high-pass filter for a time wherein an output signal representing the sum of the input signal and the delayed signal is generated and is then outputted through a second high pass filter. Output signals of the low-pass filter and the second high-pass filter are then added and the result is outputted as a signal free noise.
Inventors
- 👤 Shigeki Nishizawa
- 👤 Toshio Miyazawa
- 👤 Iwao Takemoto
- 👤 Tetsuro Izawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 13:41
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/60; H04N25/618; H04N25/70; H04N25/76; H04N25/768; H04N25/61; H04N25/615
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
164 words
A noise reduction circuit, comprising first and second circuits each consisting of a delay circuit for delaying a received periodic input signal for a predetermined time within a constant period of said input signal to provide a delay signal and an addition circuit for adding said input signal and said delay signal; a low-pass filter connected to receive an output signal from said first circuit; a first high-pass filter connected to receive an output signal from said second circuit; an integrating circuit connected to receive an output signal of the first high-pass filter and for integrating said output signal during a period of time when an addition output of said input signal and delay signal is generated; a second high-pass filter connected to receive an output signal of said integrating circuit; and an output addition circuit for adding an output of said low-pass filter and an output signal of the second high-pass filter to form an output signal from which noise has been eliminated.
Claim 2
Dependent Claim
164 words
A noise reduction circuit, comprising first and second circuits each consisting of a delay circuit for delaying a received periodic input signal for a predetermined time within a constant period of said input signal to provide a delay signal and an addition circuit for adding said input signal and said delay signal; a low-pass filter connected to receive an output signal from said first circuit; a first high-pass filter connected to receive an output signal from said second circuit; an integrating circuit connected to receive an output signal of the first high-pass filter and for integrating said output signal during a period of time when an addition output of said input signal and delay signal is generated; a second high-pass filter connected to receive an output signal of said integrating circuit; and an output addition circuit for adding an output of said low-pass filter and an output signal of the second high-pass filter to form an output signal from which noise has been eliminated.
Claim 3
Dependent Claim
62 words
The noise reduction circuit as defined in claim 1, wherein said low-pass filter produces an output signal which is limited to a band of about one-half of said constant period of said input signal, and wherein said first and second high-pass filters produce output signals which are limited to bands of one-half or more of said constant period of said input signal.
Claim 4
Dependent Claim
28 words
The noise reduction circuit as defined in claim 1 or 2, wherein said input signal supplied at a constant period is formed by an MOS solid-state imaging device.
Claim 5
Dependent Claim
183 words
A noise reduction circuit, comprising a first low-pass filter connected to receive a periodic input signal through a circuit consisting of a delay circuit for delaying signal for a predetermined time within a constant period of said input signal to produce a delay signal and an addition circuit for adding said input signal and said delay signal or said input signal; a second low-pass filter connected to received said input signal and having a cut-off frequency corresponding to the constant period; a first high-pass filter connected to receive an output signal of the second low-pass filter for passing it through a band of about half or more of said constant period; an integrating circuit connected to receive an output signal of said first high-pass filter for integrating said input signal for one constant period; a second high-pass filter connected to receive an output signal of the integrating circuit; and an output addition circuit for adding an output signal of said first low-pass filter and an output signal of the second high-pass filter to form an output signal from which noise has been eliminated.
Claim 6
Dependent Claim
183 words
A noise reduction circuit, comprising a first low-pass filter connected to receive a periodic input signal through a circuit consisting of a delay circuit for delaying signal for a predetermined time within a constant period of said input signal to produce a delay signal and an addition circuit for adding said input signal and said delay signal or said input signal; a second low-pass filter connected to received said input signal and having a cut-off frequency corresponding to the constant period; a first high-pass filter connected to receive an output signal of the second low-pass filter for passing it through a band of about half or more of said constant period; an integrating circuit connected to receive an output signal of said first high-pass filter for integrating said input signal for one constant period; a second high-pass filter connected to receive an output signal of the integrating circuit; and an output addition circuit for adding an output signal of said first low-pass filter and an output signal of the second high-pass filter to form an output signal from which noise has been eliminated.
Claim 7
Dependent Claim
33 words
The noise reduction circuit as defined in claim 4, wherein said first low-pass filter forms an output signal which is limited to a band of about one-half or less of said constant period.
Claim 8
Dependent Claim
27 words
The noise reduction circuit as defined in claim 4 or 5, wherein said input signal supplied at constant period is formed by an MOS solid-state imaging device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-11 | 1994-08-13 | 1995-02-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-11 | 1998-08-13 | 1999-02-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-11 | 2002-08-13 | 2003-02-12 | $7700.00 | Window Closed / Lapsed |