US4992771A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Chip resistor and method of manufacturing a chip resistor
Assignee: US Philips Corp
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Filing: 1989-04-05
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Granted: 1991-02-12
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Expires: 2009-04-05
Abstract
Abstract A chip resistor having a cuboid resistor body 1 of a ceramic material and solderable, metal current-supply strips 8 and 9 at a first pair of opposite side faces of the resistor body, can readily and accurately be manufactured so that it has a small resistance value, in that electrically insulating strips 6 and 7 are present between the solderable metal strips and the resistor body, and in that a second pair of opposing side faces of the resistor body is covered with electrically conductive layers 2 and 3, which layers are partly covered with electrically insulating layers 4 and 5, in such a way that each of the solderable metal strips 8 and 9 electrically conductively contacts one of the electrically conductive layers 2 and 3.
Inventors
- 👤 Didier Y. F. Caporali
- 👤 Frans L. A. Geerinckx
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 08:21
CPC Classifications
H; H01; H01C; H01C7/00; H01C17/00; H01C17/006; H01C13/00; H01C13/02
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
129 words
A chip resistor comprising a cuboid resistor body 1 of ceramic material and solderable, metal, current-supply strips 8 and 9 located at a first pair of opposite side faces of the resistor body, characterized in that electrically insulating strips 6 and 7 are present between the solderable metal strips 8 and 9 and the resistor body, and in that a second pair of opposing side faces of the resistor body is covered with electrically conductive layers 2 and 3, which layers are partly covered with electrically insulating layers 4 and 5, in such a way that each of the solderable metal strips 8 and 9 is electrically conductively connected to one of the electrically conductive layers 2 and 3, the electrically insulating layers being made of a ceramic material.
Claim 2
Dependent Claim
129 words
A chip resistor comprising a cuboid resistor body 1 of ceramic material and solderable, metal, current-supply strips 8 and 9 located at a first pair of opposite side faces of the resistor body, characterized in that electrically insulating strips 6 and 7 are present between the solderable metal strips 8 and 9 and the resistor body, and in that a second pair of opposing side faces of the resistor body is covered with electrically conductive layers 2 and 3, which layers are partly covered with electrically insulating layers 4 and 5, in such a way that each of the solderable metal strips 8 and 9 is electrically conductively connected to one of the electrically conductive layers 2 and 3, the electrically insulating layers being made of a ceramic material.
Claim 3
Independent Claim
149 words
A method of manufacturing a chip resistor, in which a cuboid resistor body is provided at two opposing side faces with metal current-supply strips, characterized in that the method comprises the following steps: a plate 1 of a ceramic resistance material is provided on both sides with electrically conductive layers 2 and 3, layers 2 and 3 are provided with electrically insulating layers 4 and 5 according to a pattern, the plate is divided into strips each strip having two large uninsulated sides, the strips are provided on the large uninsulated sides with electrically insulating strips 6 and 7, the strips are provided with solderable metal strips 8 and 9 on top of the electrically insulating strips 6 and 7, each of the metal strips 8 and 9 being electrically conductively connected to one of the electrically conductive layers 2 and 3, and the strips are divided into cuboids.
Claim 4
Independent Claim
149 words
A method of manufacturing a chip resistor, in which a cuboid resistor body is provided at two opposing side faces with metal current-supply strips, characterized in that the method comprises the following steps: a plate 1 of a ceramic resistance material is provided on both sides with electrically conductive layers 2 and 3, layers 2 and 3 are provided with electrically insulating layers 4 and 5 according to a pattern, the plate is divided into strips each strip having two large uninsulated sides, the strips are provided on the large uninsulated sides with electrically insulating strips 6 and 7, the strips are provided with solderable metal strips 8 and 9 on top of the electrically insulating strips 6 and 7, each of the metal strips 8 and 9 being electrically conductively connected to one of the electrically conductive layers 2 and 3, and the strips are divided into cuboids.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-11 | 1994-08-13 | 1995-02-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-11 | 1998-08-13 | 1999-02-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-11 | 2002-08-13 | 2003-02-12 | $7700.00 | Window Closed / Lapsed |