Low offset transconductance amplifier in an analog electronic cochlea

Claim 2

A low offset transconductance amplifier comprising: first and second differentially connected input transistors; an output current source transistor; an output current sink transistor; first means for inducing a current in said output current source transistor in response to said first input transistor, said first input transistor having a main conduction path, and said first current inducing means comprising a current mirror including a first current mirror transistor having a main conduction path coupled in series with said main conduction path of said first input transistor, and the junction of said main conduction paths of said first input transistor and said first current mirror transistor being coupled to control electrodes of said first current mirror transistor and said output current source transistor; and second means for inducing a current in said output current sink transistor in response to said second input transistor, including a cascode transistor.

Claim 3

A low offset transconductance amplifier comprising: first and second differentially connected input transistors; an output current source transistor; an output current sink transistor; first means for inducing a current in said output current source transistor in response to said first input transistor; and second means for inducing a current in said output current sink transistor in response to said second input transistor, including a cascode transistor, wherein said second current inducing means comprises: a first current mirror for coupling said second input transistor to a first current path; said cascode transistor, having a main conduction path coupled in said first current path; and a second current mirror for coupling said current path to said output current sink transistor.

Claim 4

A low offset transconductance amplifier comprising: first and second differentially connected input transistors; an output current source transistor; an output current sink transistor; first means for inducing a current in said output current source transistor in response to said first input transistor; and second means for inducing a current in said output current sink transistor in response to said second input transistor, including a cascode transistor, wherein said second current inducing means comprises: a first current mirror for coupling said second input transistor to a first current path; said cascode transistor, having a main conduction path coupled in said first current path; and a second current mirror for coupling said current path to said output current sink transistor.

Claim 5

The amplifier of claim 2, wherein: said second input transistor has a main conduction path; and said first current mirror includes: a first transistor, having a main conduction path coupled in series with said main conduction path of said second input transistor; and a second transistor, having a main conduction path coupled in said first current path; wherein the junction of said main conduction paths of said second input transistor and said first transistor of said first current mirror is coupled to control electrodes of said first and second transistors of said first current mirror; and said second current mirror includes: a first transistor, having a main conduction path coupled in said first current path; and said output current sink transistor; wherein the junction of said main conduction paths of said cascode transistor and said first transistor of said second current mirror is coupled to control electrodes of said first transistor of said second current mirror, and said output current sink transistor.

Claim 6

The amplifier of claim 2, wherein said first current inducing means comprises a third current mirror for coupling said first input transistor to said output current source transistor.

Claim 7

The amplifier of claim 4, wherein: said first input transistor has a main conduction path; and said third current mirror includes: a first transistor, having a main conduction path coupled in series with said main conduction path of said first input transistor; and said output current source transistor; wherein the junction of said main conduction paths of said first transistor of said third current mirror and said first input transistor is coupled to control electrodes of said first transistor of said third current mirror and said other one of said input transistors.

Claim 8

A low offset transconductance amplifier comprising: first and second differentially connected input transistors; an output current source transistor; an output current sink transistor; first means for inducing a current in said output current source transistor in response to said fist input transistor; second means for inducing a current in said output current sink transistor in response to said second input transistor, including a cascode transistor; and a bias source coupled to said cascode transistor, wherein said bias source comprises a first and a second transistor having respective main conduction paths serially coupled between a source of operating potential and a source of reference potential; and wherein the junction of said main conduction paths of said first and second bias transistors is coupled to control electrodes of said first bias transistor and said cascode transistor.

Claim 9

A low offset transconductance amplifier comprising: first and second differentially connected input transistors; an output current source transistor; an output current sink transistor; first means for inducing a current in said output current source transistor in response to said fist input transistor; second means for inducing a current in said output current sink transistor in response to said second input transistor, including a cascode transistor; and a bias source coupled to said cascode transistor, wherein said bias source comprises a first and a second transistor having respective main conduction paths serially coupled between a source of operating potential and a source of reference potential; and wherein the junction of said main conduction paths of said first and second bias transistors is coupled to control electrodes of said first bias transistor and said cascode transistor.

Claim 10

The amplifier of claim 6, further including: a current setting transistor, having a main conduction path serially coupled with said differentially connected input transistors between said source of operating potential and said source of reference potential; wherein: a source of bias control signal is coupled to control electrodes of said second bias transistor and said current setting transistor.

Claim 11

A low offset transconductance amplifier, in an analog electronic cochlea including a plurality of serially coupled transmission line stages, comprising: a first and a second transistor, having serially connected main conduction paths; a third and a fourth transistor, having serially connected main conduction paths, connected in parallel with said main conduction paths of said first and second transistors; a fifth transistor, having a main conduction path serially connected with said parallel connection of said first, second, third and fourth transistors between a source of operating potential and a source of reference potential; a sixth and a seventh transistor, having serially connected main conduction paths between said source of operating potential and said source of reference potential; an eighth, a ninth and a tenth transistor having serially connected main conduction paths coupled between said source of operating potential and said source of reference potential; an eleventh and a twelfth transistor having serially connected main conduction paths coupled between said source of operating potential and said source of reference potential; wherein: the junction of said main conduction paths of said first and second transistor is coupled to control electrodes of said first and sixth transistors; the junction of said main conduction paths of said third and fourth transistors is coupled to control electrodes of said third and eighth transistors; the junction of said main conduction paths of said ninth and tenth transistors is coupled to control electrodes of said seventh and tenth transistors; the junction of said main conduction paths of said eleventh and twelfth transistors is coupled to control electrodes of said eighth and eleventh transistor; a source of bias signal is coupled to control electrodes of said fifth and twelfth transistors; an input terminal is coupled to a control electrode of said fourth transistor; the junction of said main conduction paths of said sixth and seventh transistors is coupled to an output terminal, and to a control electrode of said fourth transistor.

Claim 12

A low offset transconductance amplifier, in an analog electronic cochlea including a plurality of serially coupled transmission line stages, comprising: a first and a second transistor, having serially connected main conduction paths; a third and a fourth transistor, having serially connected main conduction paths, connected in parallel with said main conduction paths of said first and second transistors; a fifth transistor, having a main conduction path serially connected with said parallel connection of said first, second, third and fourth transistors between a source of operating potential and a source of reference potential; a sixth and a seventh transistor, having serially connected main conduction paths between said source of operating potential and said source of reference potential; an eighth, a ninth and a tenth transistor having serially connected main conduction paths coupled between said source of operating potential and said source of reference potential; an eleventh and a twelfth transistor having serially connected main conduction paths coupled between said source of operating potential and said source of reference potential; wherein: the junction of said main conduction paths of said first and second transistor is coupled to control electrodes of said first and sixth transistors; the junction of said main conduction paths of said third and fourth transistors is coupled to control electrodes of said third and eighth transistors; the junction of said main conduction paths of said ninth and tenth transistors is coupled to control electrodes of said seventh and tenth transistors; the junction of said main conduction paths of said eleventh and twelfth transistors is coupled to control electrodes of said eighth and eleventh transistor; a source of bias signal is coupled to control electrodes of said fifth and twelfth transistors; an input terminal is coupled to a control electrode of said fourth transistor; the junction of said main conduction paths of said sixth and seventh transistors is coupled to an output terminal, and to a control electrode of said fourth transistor.

Claim 13

In an analog electronic cochlea including a plurality of serially coupled transmission line stages, wherein each transmission line stage operates as a second-order low pass filter section and includes a low transconductance amplifier therein, the improvement wherein said low transconductance amplifier comprises: first and second differentially connected input transistors; an output current source transistor; an output current sink transistor; first means for inducing a current in said output current source transistor in response to said first input transistor; and second means for inducing a current in said output current sink transistor in response to said second input transistor, including a cascode transistor, wherein said second current inducing means comprises: a first current mirror for coupling said second input transistor to a first current path; said cascode transistor, having a main conduction path coupled in said first current path; and a second current mirror for coupling said current path to said output current sink transistor.

Claim 14

In an analog electronic cochlea including a plurality of serially coupled transmission line stages, wherein each transmission line stage operates as a second-order low pass filter section and includes a low transconductance amplifier therein, the improvement wherein said low transconductance amplifier comprises: first and second differentially connected input transistors; an output current source transistor; an output current sink transistor; first means for inducing a current in said output current source transistor in response to said first input transistor; and second means for inducing a current in said output current sink transistor in response to said second input transistor, including a cascode transistor, wherein said second current inducing means comprises: a first current mirror for coupling said second input transistor to a first current path; said cascode transistor, having a main conduction path coupled in said first current path; and a second current mirror for coupling said current path to said output current sink transistor.