Trench gate structure with thick bottom oxide

Claim 1

A method of fabricating a trench gate semiconductor device comprising the steps of: (a) providing a silicon semiconductor wafer of a first type conductivity; (b) growing a thermal oxide layer on a first major surface of said wafer; (c) depositing a thin silicon nitride layer on said thermal oxide layer; (d) ion implanting a second conductivity type dopant through said oxide and nitride layers into the underlying silicon; (e) forming and patterning a reactive ion etching masking layer over said nitride layer to define a trench location; (f) reactive ion etching a trench into said silicon material; (g) implanting oxygen ions into the bottom wall of said trench; (h) thermal annealing said second conductivity type implanted region and said oxygen implanted region, respectively, to form the desired second conductivity type region and silicon oxide; (i) removing damaged material from the sidewalls of said trench and any silicon on the bottom of said trench over said silicon oxide; (j) growing a thin gate oxide layer on the sidewalls of said trench; (k) filling said trench with conductive gate material; (l) planarizing said wafer by removing said conductive gate material from over said reactive ion etching mask; (m) removing said reactive ion etching mask; (n) forming a first conductivity type region in said second conductivity type region adjacent said first major surface of said wafer; and (o) forming metallic electrodes on said device.

Claim 2

A method of fabricating a trench gate semiconductor device comprising the steps of: (a) providing a silicon semiconductor wafer of a first type conductivity; (b) growing a thermal oxide layer on a first major surface of said wafer; (c) depositing a thin silicon nitride layer on said thermal oxide layer; (d) ion implanting a second conductivity type dopant through said oxide and nitride layers into the underlying silicon; (e) forming and patterning a reactive ion etching masking layer over said nitride layer to define a trench location; (f) reactive ion etching a trench into said silicon material; (g) implanting oxygen ions into the bottom wall of said trench; (h) thermal annealing said second conductivity type implanted region and said oxygen implanted region, respectively, to form the desired second conductivity type region and silicon oxide; (i) removing damaged material from the sidewalls of said trench and any silicon on the bottom of said trench over said silicon oxide; (j) growing a thin gate oxide layer on the sidewalls of said trench; (k) filling said trench with conductive gate material; (l) planarizing said wafer by removing said conductive gate material from over said reactive ion etching mask; (m) removing said reactive ion etching mask; (n) forming a first conductivity type region in said second conductivity type region adjacent said first major surface of said wafer; and (o) forming metallic electrodes on said device.

Claim 4

A method of fabricating a trench gate semiconductor device comprising the steps of: (a) providing a silicon semiconductor wafer of a first type conductivity; (b) growing a thermal oxide layer on a first major surface of said wafer; (c) depositing a thin silicon nitride layer over said thermal oxide layer; (d) ion implanting a second conductivity type dopant through said oxide and nitride layers into the underlying silicon of said wafer; (e) annealing said implanted dopant to form a desired second conductivity type region; (f) forming and patterning a reactive ion etching masking layer over said nitride layer to define a trench location; (g) reactive ion etching a trench into said silicon material; (h) removing damaged surface material from the walls of said trench; (i) growing a thin gate oxide on the walls of said trench; (j) forming a protective layer on the sidewalls of said trench; (k) growing a thick oxide layer at the bottom of said trench; (l) removing said protective layer from said sidewalls; (m) filling said trench with conductive gate material; (n) planarizing said wafer to expose said reactive ion etching masking layer; (o) removing said reactive ion etching mask; (p) forming a first conductivity source region in said second conductivity type region adjacent said first major surface of said wafer; and (q) forming metallic electrodes on said device.

Claim 5

A method of fabricating a trench gate semiconductor device comprising the steps of: (a) providing a silicon semiconductor wafer of a first type conductivity; (b) growing a thermal oxide layer on a first major surface of said wafer; (c) depositing a thin silicon nitride layer over said thermal oxide layer; (d) ion implanting a second conductivity type dopant through said oxide and nitride layers into the underlying silicon of said wafer; (e) annealing said implanted dopant to form a desired second conductivity type region; (f) forming and patterning a reactive ion etching masking layer over said nitride layer to define a trench location; (g) reactive ion etching a trench into said silicon material; (h) removing damaged surface material from the walls of said trench; (i) growing a thin gate oxide on the walls of said trench; (j) forming a protective layer on the sidewalls of said trench; (k) growing a thick oxide layer at the bottom of said trench; (l) removing said protective layer from said sidewalls; (m) filling said trench with conductive gate material; (n) planarizing said wafer to expose said reactive ion etching masking layer; (o) removing said reactive ion etching mask; (p) forming a first conductivity source region in said second conductivity type region adjacent said first major surface of said wafer; and (q) forming metallic electrodes on said device.