US4989256A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-organizing circuits
Assignee: Individual
•
Filing: 1988-07-06
•
Granted: 1991-01-29
•
Expires: 2008-07-06
Abstract
Abstract Self-organizing circuits to receive input signals from transducers and the like and operable, under guidance from modifying inputs thereto, operate in a learning mode and systems embodying such self-organizing circuits. The circuits include mechanisms to change the modifying inputs based upon Boolean functions and further mechanisms to change the modifying inputs based upon competition among the input signals. The circuits have time delays which allow identification of time-varying patterns. The circuits also further mechanisms to change the modifying inputs based on a balance of inhibitory and excitory influences on subcircuits and based on changes in the messages between subcircuits.
Inventors
- 👤 Bruce S. Buckley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 04:07
CPC Classifications
G; G09; G09B; G09B25/00; G09B25/02
Claims Analysis
Total Claims: 55
Claim 1
Independent Claim
228 words
A system that comprises: transducer means to sense an input thereto and operable to provide a first output signal representative of said input; self-organizing circuit means connected to receive said first output signal and operable to effect analysis of constituent elements of said input and provide a further output signal related to said input, each self-organizing circuit of said self-organizing circuit means including a plurality of sub-circuits or levels which are connected to receive messages from some other sub-circuit or level and are operable to deliver messages to some other sub-circuit or level, there being voting in that each sub-circuit or level weights relative amounts of negative and positive influence thereto and votes whether or not to pass along information to the further sub-circuits or levels; and error correcting means acting on each subcircuit or level of the self-organizing circuit means which serves to correct errors in said further output signal by modifying the strength of the connections between said sub-circuits or levels occasioned by inaccurate analysis of the input by the self-organizing circuit means, and for effecting analysis of a first pattern of constituent elements and at a later time to apply said error correcting means to effect analysis of a second pattern of constituent elements without modifying the strength of at least a portion of said connections made during said first application of error correcting means.
Claim 2
Independent Claim
228 words
A system that comprises: transducer means to sense an input thereto and operable to provide a first output signal representative of said input; self-organizing circuit means connected to receive said first output signal and operable to effect analysis of constituent elements of said input and provide a further output signal related to said input, each self-organizing circuit of said self-organizing circuit means including a plurality of sub-circuits or levels which are connected to receive messages from some other sub-circuit or level and are operable to deliver messages to some other sub-circuit or level, there being voting in that each sub-circuit or level weights relative amounts of negative and positive influence thereto and votes whether or not to pass along information to the further sub-circuits or levels; and error correcting means acting on each subcircuit or level of the self-organizing circuit means which serves to correct errors in said further output signal by modifying the strength of the connections between said sub-circuits or levels occasioned by inaccurate analysis of the input by the self-organizing circuit means, and for effecting analysis of a first pattern of constituent elements and at a later time to apply said error correcting means to effect analysis of a second pattern of constituent elements without modifying the strength of at least a portion of said connections made during said first application of error correcting means.
Claim 3
Dependent Claim
38 words
A system as claimed in claim 1 which includes error correcting means which modify the strength of the connections between said sub-circuits or levels based at least partially upon the balance between negative and positive influences of voting.
Claim 4
Dependent Claim
22 words
A system as claimed in claim 2 in which each sub-circuit or level provides path reinforcement to the other sub-circuits or levels.
Claim 5
Dependent Claim
124 words
A system as claimed in claim 3 in which the self-organizing circuit further includes a preprocessor circuit connected to receive said first output signal as input thereto, which preprocessor is adapted to process said input to provide better prior organization of said first output signal to improve or simplify the analysis of constituent elements thereof, the thus-organized signal being connected as input to said plurality of sub-circuits or levels, the connection being such that the inputs to the successive sub-circuits or levels are serial in that a signal to a particular sub-circuit or level is modified by that particular sub-circuit or level and then passed along to successive sub-circuits or levels, or the signal is passed along to successive sub-circuit or level without modifications.
Claim 6
Independent Claim
206 words
A system that comprises: transducer means to sense as input thereto a signal containing information, said transducer means being operable to convert that input to a first output signal representative of said input; self-organizing circuit means connected to receive said first output signal and operable to effect analysis of the pattern of constituent elements thereof and provide a second output signal shaped, at least in part, by said information, said self-organizing circuit means comprising multi-levels with punish and reward signals to all levels, feedback signals at all levels and random initial output weighting; and error correcting means acting on each subcircuit or level of the self-organizing circuit means which serves to correct errors in said second output signal by modifying the strength of the connections between said sub-circuits or levels occasioned by inaccurate analysis of the input by the self-organizing circuit means, which error correcting means include said punish and reward signals as input and which effect analysis of a first pattern of constituent elements and, at a later time, apply said error correcting means to effect analysis of a second pattern of constituent elements without modifying the strength of at least a portion of said connections made during said first application of error correcting means.
Claim 7
Independent Claim
206 words
A system that comprises: transducer means to sense as input thereto a signal containing information, said transducer means being operable to convert that input to a first output signal representative of said input; self-organizing circuit means connected to receive said first output signal and operable to effect analysis of the pattern of constituent elements thereof and provide a second output signal shaped, at least in part, by said information, said self-organizing circuit means comprising multi-levels with punish and reward signals to all levels, feedback signals at all levels and random initial output weighting; and error correcting means acting on each subcircuit or level of the self-organizing circuit means which serves to correct errors in said second output signal by modifying the strength of the connections between said sub-circuits or levels occasioned by inaccurate analysis of the input by the self-organizing circuit means, which error correcting means include said punish and reward signals as input and which effect analysis of a first pattern of constituent elements and, at a later time, apply said error correcting means to effect analysis of a second pattern of constituent elements without modifying the strength of at least a portion of said connections made during said first application of error correcting means.
Claim 8
Independent Claim
167 words
A system that comprises: self-organizing circuit means connected to receive as input information in the form of a signal and operable to effect analysis of the pattern of constituent elements thereof to extract said information from the input signal and provide an output signal related to said information, said self-organizing circuit means comprising multi-level circuits, error correcting means acting on each sub-circuit or level of the self-organizing circuit means which serves to correct errors in said second output signal by modifying the strength of the connections between said sub-circuits or levels occasioned by inaccurate analysis of the input by the self-organizing circuit means, which error correcting means include said punish and reward signals as input and which effect analysis of a first pattern of constituent elements and, at a later time, apply said error correcting means to effect analysis of a second pattern of constituent elements without modifying the strength of at least a portion of said connections made during said first application of error correcting means.
Claim 9
Independent Claim
167 words
A system that comprises: self-organizing circuit means connected to receive as input information in the form of a signal and operable to effect analysis of the pattern of constituent elements thereof to extract said information from the input signal and provide an output signal related to said information, said self-organizing circuit means comprising multi-level circuits, error correcting means acting on each sub-circuit or level of the self-organizing circuit means which serves to correct errors in said second output signal by modifying the strength of the connections between said sub-circuits or levels occasioned by inaccurate analysis of the input by the self-organizing circuit means, which error correcting means include said punish and reward signals as input and which effect analysis of a first pattern of constituent elements and, at a later time, apply said error correcting means to effect analysis of a second pattern of constituent elements without modifying the strength of at least a portion of said connections made during said first application of error correcting means.
Claim 10
Dependent Claim
44 words
A system as claimed in claim 6 which includes error correcting means which modify the strength of connections between sub-circuits of said level circuits based at least partially upon the balance between the combined strength of negative and positive connections made between said sub-circuits.
Claim 11
Independent Claim
175 words
A system that comprises: self-organizing circuit means connected to receive a plurality of input signals representing constituent elements of input information and operable to effect identification of the pattern of constituent elements by combining the influence which each constituent element has on the pattern of constituent elements, said self-organizing circuit means comprising multi-levels with feedback from higher levels to lower levels to aid in identification of said pattern, said self-organizing circuit means being operable to provide an output signal related to said pattern; and error correction means connected to modify said self-organizing circuit means by varying the influence which each constituent element has on a first pattern of constituent elements as occasioned by accurate and inaccurate identification of said input information and said error correction means further connected to hold fixed at least some portion of the influence which each constituent element has on said first pattern while varying the influence which each constituent element has on a second pattern of constituent elements as occasioned by accurate and inaccurate identification of said second input information.
Claim 12
Independent Claim
175 words
A system that comprises: self-organizing circuit means connected to receive a plurality of input signals representing constituent elements of input information and operable to effect identification of the pattern of constituent elements by combining the influence which each constituent element has on the pattern of constituent elements, said self-organizing circuit means comprising multi-levels with feedback from higher levels to lower levels to aid in identification of said pattern, said self-organizing circuit means being operable to provide an output signal related to said pattern; and error correction means connected to modify said self-organizing circuit means by varying the influence which each constituent element has on a first pattern of constituent elements as occasioned by accurate and inaccurate identification of said input information and said error correction means further connected to hold fixed at least some portion of the influence which each constituent element has on said first pattern while varying the influence which each constituent element has on a second pattern of constituent elements as occasioned by accurate and inaccurate identification of said second input information.
Claim 13
Dependent Claim
47 words
A system as in claim 8 which includes error correcting means which vary the influence each constituent element has on the pattern of constituent elements based at least partially upon the balance of said combining of negative and positive influences of sub-circuits of said self-organizing circuit means.
Claim 14
Dependent Claim
37 words
A system as in claim 8 in which said self-organizing circuit means effects identification among a plurality of possible patterns of constituent elements of input information and provides a plurality of output signals based on said identification.
Claim 15
Dependent Claim
31 words
A system as in claim 8 in which said self-organizing circuit means uses primarily digital means for combining the influence which each constituent element has on the pattern of constituent elements.
Claim 16
Dependent Claim
32 words
A system as in claim 8 in which self-organizing circuit means receives time-varying input information and whose identification of the pattern of constituent elements of said input information also varies with time.
Claim 17
Dependent Claim
30 words
A system as in claim 8 in which said self-organizing circuit means effects said identification of said patterns by simultaneously combining the influence of constituent elements of said input information.
Claim 18
Dependent Claim
30 words
A system as in claim 8 in which said self-organizing circuit means effects said identification of said patterns by sequentially combining the influence of constituent elements of said input information.
Claim 19
Dependent Claim
42 words
A system as in claim 8 in which said error correction means varies the influence which each constituent element has on said patterns of constituent elements by non-electrical means including but not limited to pnuematic, hydraulic, chemical, optical, magnetic or electrostatic means.
Claim 20
Dependent Claim
24 words
A system as in claim 8 in which the input information is non-electrical and is transduced to electrical input information by electronic transducer means.
Claim 21
Dependent Claim
76 words
A system as in claim 8 in which a plurality of said self-organizing means are organized such that the output of one self-organizing circuit becomes part of the input information for another self-organizing circuit and said error correction means varies the influence which each constituent element has on the pattern of constituent elements of each said self-organizing circuit based on the accurate and inaccurate identification of input information of any of the plurality of self-organizing circuits.
Claim 22
Dependent Claim
35 words
A system as in claim 8 in which is incorporated into a device which uses said identification of the pattern of constituent elements of input information to alter the input information received by the device.
Claim 23
Dependent Claim
26 words
A system as in claim 8 in which the varying influence which each constituent element has on the patterns of constituent elements is initially chosen randomly.
Claim 24
Dependent Claim
53 words
A system as in claim 8 in which the self-organizing circuit further includes preprocessor circuit connected to receive said plurality of input signals as input thereto, which preprocessor is adapted to process said input signals to provide constituent elements of said input information which improve or simplify the identification of said input information.
Claim 25
Dependent Claim
62 words
A system according to claim 1 in which each self-organizing circuit of the self-organizing circuit means is an analog circuit and in which voting is implemented by a multiple-input voting circuit that receives input electrical currents and produces an output that is proportional to the sum of the input currents, the output of the analog circuit being a function of said sum.
Claim 26
Dependent Claim
41 words
A system according to claim 21 which includes error correcting means which modify the strength of the input electrical currents to said multiple-input voting circuit based at least partially upon the balance between negative and positive influences of said voting circuit.
Claim 27
Dependent Claim
90 words
A system according to claim 21 in which each sub-circuit or level comprises a plurality of DACs and associated voting circuits combined to form a sub-circuit or level, said DACs including path-related DACs which either add or draw electric current to the voting circuit associated therewith and threshold DACs which draw current from the associated voting circuit, the outputs of the plurality of voting circuits being the output of the sub-circuit or level and being combined with like outputs from other sub-circuits or levels to form said further output signal.
Claim 28
Dependent Claim
71 words
A system according to claim 23 in which the error correcting means which modify the strength of the connections between said sub-circuits or levels is a computer connected to receive said further output signal and programmed to interact with the selforganizing circuit means in a learning mode, said computer being operable to provide signals which alter the amount of electric current which said DACs add or draw from said voting circuit.
Claim 29
Dependent Claim
50 words
A system according to claim 24 that includes a preprocessor that is connected to receive said first output signal as input thereto, which preprocessor is adapted to process said input to provide better prior organization of said first output signal to improve or simplify the analysis of constituent elements thereof.
Claim 30
Dependent Claim
54 words
A system according to claim 24 in which the inputs and outputs of said level circuits are monitored by the computer, said inputs being compared with said outputs to determine cumulative Boolean functions thereof, and error correcting means of the selforganizing circuit means are based, in part, on competition for said cumulative Boolean functions.
Claim 31
Dependent Claim
49 words
A system according to claim 26 wherein each path-related DAC comprises a binary up-down counter wherein error correcting means is effected by altering the value of the binary numbers in the counter, thereby to decrease or increase electric current flow into the voting circuit associated with the particular DAC.
Claim 32
Dependent Claim
44 words
A system according to claim 27 wherein said error correcting means is based, at least partially, upon the balance between DACs which add electric current and DACs which draw electric current from the voting circuit associated therewith in the course of a learning experience.
Claim 33
Dependent Claim
41 words
A system according to claim 1 in which each sub-circuit or level comprises a plurality of positive-negative DACs, each positive-negative DAC being associated with a voting circuit and being adapted to apply and modify electric current to the associated voting circuit.
Claim 34
Dependent Claim
82 words
A system according to claim 29 in which each said DAC includes a binary up-down counter which applies positive current flow when connected to a positive voltage source and negative flow when connected to a negative voltage source, which system includes a computer to apply, during a learning mode, reward signals by adding binary bits to increase the value of the binary number stored in the counter and punishment signals by subtracting binary bits from the binary number stored in the counter.
Claim 35
Dependent Claim
46 words
A system according to claim 8 in which the error correction means includes means to deliver punish and reward signals to the self-organizing circuit means based, in part, upon competition for cumulative Boolean functions between the input signals to each said multilevel circuit and its outputs.
Claim 36
Dependent Claim
32 words
A system according to claim 31 wherein the punish and reward signals are based, in part, on universal signals, that is, signals that are delivered simultaneously to all levels of said multi-levels.
Claim 37
Dependent Claim
58 words
A system according to claim 8 that includes weighting means that includes a plurality of DACs, wherein initial weighting of those DACs not held fixed is achieved by randomly loading these DACs, and that includes reward and punish circuit means to add to and subtract from the binary numbers in the DACs on the basis of said indentification.
Claim 38
Dependent Claim
36 words
A system according to claim 5 wherein the self-organizing circuit means includes a plurality of DACs to permit weighting, weighting being achieved by introducing binary numbers to the DACs which regulate the strength of said connections.
Claim 39
Dependent Claim
43 words
A system according to claim 34 wherein the DACs are positive/negative DACs in that each connection comprises at least one of a DAC which adds electric current and a DAC which draws electric current in relation to the value of said binary number.
Claim 40
Dependent Claim
37 words
A system according to claim 6 wherein feedback paths are provided to permit feedback signals to flow from the output of the higher-level circuit to the input to the lower-level circuit to enhance analysis of the patterns.
Claim 41
Dependent Claim
62 words
A system according to claim 36 wherein the multi-level circuits consist of several circuits that proceed from a lowest level circuit to an Nth or highest level circuit, wherein each level circuit includes a plurality of binary-weighted DACs, each of which comprises a binary digital counter, wherein weighting of said output signal is achieved by controlling a binary-digital input to said counter.
Claim 42
Dependent Claim
48 words
A system according to claim 37 wherein initial weighting of those connections not held fixed is achieved by means that loads the counter with small, but random, binary numbers, the punish and reward signals being applied by either adding or subtracting numbers from the counter to achieve learning.
Claim 43
Dependent Claim
35 words
A system according to claim 38 in which said punish and reward signals are based, in part, upon competition for cumulative Boolean functions between the input signals to each said multilevel circuit and its outputs.
Claim 44
Dependent Claim
32 words
A system according to claim 39 wherein said punish and reward signals are based, in part, on universal signals, that is, signals that are delivered simultaneously to all levels of said multi-levels.
Claim 45
Dependent Claim
44 words
A system according to claim 40 wherein said punish and reward signals are based, in part, upon the balance between DACs which add electric current and DACs which draw electric current from the voting circuit associated therewith in the course of a learning experience.
Claim 46
Dependent Claim
43 words
A system according to claim 1 wherein feedback means is provided to permit feedback signals to flow from the output of a higher sub-circuit or level to the input of a lower sub-circuit or level to enhance analysis of said first output signal.
Claim 47
Dependent Claim
47 words
A system according to claim 42 in which initial weights of those connections between each sub-circuit or level not held fixed are randomly applied and in which said error correcting means include punish and reward signals, said system including means to apply said punish and reward signals.
Claim 48
Dependent Claim
31 words
A system according to claim 8 in which said each constituent element is delayed in time before combining the influence which each constituent element has on the patterns of constituent elements.
Claim 49
Independent Claim
200 words
A system that comprises: transducer means to sense an input thereto and operable to provide a first output signal representative of said input; self-organizing circuit means connected to receive said first output signal and operable to effect analysis of constituent elements of said input and provide a further output signal related to said input, each self-organizing circuit of said self-organizing circuit means including a plurality of sub-circuits or levels which are connected to receive messages from some other sub-circuit or level and are operable to deliver messages to some other sub-circuit or level, there being voting in that each sub-circuit or level weights relative amounts of negative and positive inputs thereto and votes whether or not to pass along information to the further sub-circuits or levels; and error correcting means acting on each subcircuit or level of the self-organizing circuit means which serves to correct errors in said further output signal by modifying the strength of the connections between said sub-circuits or levels occasioned by inaccurate analysis of the input by the self-organizing circuit means, and wherein said modifying the strength of connections is based at least partially upon the balance between said negative and positive weighting of said inputs.
Claim 50
Independent Claim
200 words
A system that comprises: transducer means to sense an input thereto and operable to provide a first output signal representative of said input; self-organizing circuit means connected to receive said first output signal and operable to effect analysis of constituent elements of said input and provide a further output signal related to said input, each self-organizing circuit of said self-organizing circuit means including a plurality of sub-circuits or levels which are connected to receive messages from some other sub-circuit or level and are operable to deliver messages to some other sub-circuit or level, there being voting in that each sub-circuit or level weights relative amounts of negative and positive inputs thereto and votes whether or not to pass along information to the further sub-circuits or levels; and error correcting means acting on each subcircuit or level of the self-organizing circuit means which serves to correct errors in said further output signal by modifying the strength of the connections between said sub-circuits or levels occasioned by inaccurate analysis of the input by the self-organizing circuit means, and wherein said modifying the strength of connections is based at least partially upon the balance between said negative and positive weighting of said inputs.
Claim 51
Dependent Claim
24 words
A system according to claim 1 in which said error correcting means include means to sensitize said self-organizing circuit to changes in said input.
Claim 52
Dependent Claim
42 words
A system according to claim 5 in which said error correcting means acting to modify the strength of said connections to correct errors in said second output signal include means to make said analysis more sensitive to changes in all said levels.
Claim 53
Dependent Claim
25 words
A system according to claim 6 in which said error correcting means includes means to sensitize said self-organizing circuit to changes in said input information.
Claim 54
Dependent Claim
35 words
A system according to claim 8 in which said error correcting means include means to sensitize said self-organizing circuit to changes in said input signals represented by changes in the constituent elements of input information.
Claim 55
Dependent Claim
28 words
A system according to claim 45 in which said error correcting means include means to sensitize said self-organizing circuit to changes in said messages between sub-circuits or levels.
References Cited (Backward Citations)
US4479241A
Cited
US4774677A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-28 | 1994-07-30 | 1995-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-28 | 1998-07-30 | 1999-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-28 | 2002-07-30 | 2003-01-29 | $7700.00 | Window Closed / Lapsed |