US4985893A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit testing apparatus
Assignee: Individual
•
Filing: 1989-03-03
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Granted: 1991-01-15
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Expires: 2009-03-03
Abstract
Abstract Generally there is provided a ROM memory arranged to be inserted in place of a pre-existing ROM on the microprocessor based circuit board under test, wherein the ROM contains specific test sequences programmed therein. The test apparatus further includes a microprocessor control, a keypad, a display and an interface. On start up the circuit under test runs programs stored in the inserted ROM and outputs on the data bus information relative to the results. During some tests the circuit is held in a wait state to allow probing of the circuit under test for logic errors. In an operator programmed test mode the operator may cause the system to read and write data in response to entries from the keypad.
Inventors
- 👤 Daniel Gierke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 04:15
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F11/273; G06F11/277
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
216 words
An electronic testing apparatus for testing a microprocessor based circuit, said circuit under test including a microprocessor, a ROM memory and a communication bus, the test apparatus comprising: a control unit including a microprocessor, a display, memory means, and a communication bus, wherein said control unit is arranged to receive diagnostic test results and display information responsive thereto; an interface unit coupled to the communication bus of said control unit and to said communication bus of said circuit under test, said interface unit being arranged to respond to said control unit and to said circuit under test and to transmit data therebetween; an insertable ROM memory arranged to be inserted into the circuit under test in place of the pre-existing ROM memory, said insertable ROM memory being programmed with instructions operable by the microprocessor of the circuit under test for testing the circuit under test and providing data output indicating the results of the test; and wait state test circuitry including a counter responsive to a memory read instruction, circuit means for generating a "Ready" signal to the microprocessor of the circuit under test in response to the memory read instruction and to the state of said counter, such that the "Ready" signal holds the wait state for extended duration if the wait state is operational.
Claim 2
Dependent Claim
216 words
An electronic testing apparatus for testing a microprocessor based circuit, said circuit under test including a microprocessor, a ROM memory and a communication bus, the test apparatus comprising: a control unit including a microprocessor, a display, memory means, and a communication bus, wherein said control unit is arranged to receive diagnostic test results and display information responsive thereto; an interface unit coupled to the communication bus of said control unit and to said communication bus of said circuit under test, said interface unit being arranged to respond to said control unit and to said circuit under test and to transmit data therebetween; an insertable ROM memory arranged to be inserted into the circuit under test in place of the pre-existing ROM memory, said insertable ROM memory being programmed with instructions operable by the microprocessor of the circuit under test for testing the circuit under test and providing data output indicating the results of the test; and wait state test circuitry including a counter responsive to a memory read instruction, circuit means for generating a "Ready" signal to the microprocessor of the circuit under test in response to the memory read instruction and to the state of said counter, such that the "Ready" signal holds the wait state for extended duration if the wait state is operational.
Claim 3
Dependent Claim
26 words
The electronic testing apparatus of claim 1 further comprising means for monitoring the output of the counter to indicate faulty early termination of the wait state.
Claim 4
Dependent Claim
221 words
An electronic testing apparatus for testing a microprocessor based circuit, said circuit under test including a microprocessor, a ROM memory and a communication bus, the testing apparatus comprising: a control unit including a microprocessor, a display, memory means, and a communication bus, wherein said control unit is arranged to receive diagnostic test results and display information responsive thereto; an interface unit coupled to the communication bus of said control unit and to said communication bus of said circuit under test, said interface unit being arranged to respond to said control unit and to said circuit under test and to transmit data therebetween; an insertable ROM memory arranged to be inserted into the circuit under test in place of the pre-existing ROM memory, said insertable ROM memory being programmed with instructions operable by the microprocessor of the circuit under test for testing the circuit under test and providing data output indicating the results of the test; and input means in said control unit and further comprising program means in said insertable ROM for causing the microprocessor in the circuit under test to: (a) read from said input means; (b) read and write data to selected ports in response to said input; (c) verify the data following said read and write operations; (d) transmit to said display means the results of said verification.
Claim 5
Dependent Claim
221 words
An electronic testing apparatus for testing a microprocessor based circuit, said circuit under test including a microprocessor, a ROM memory and a communication bus, the testing apparatus comprising: a control unit including a microprocessor, a display, memory means, and a communication bus, wherein said control unit is arranged to receive diagnostic test results and display information responsive thereto; an interface unit coupled to the communication bus of said control unit and to said communication bus of said circuit under test, said interface unit being arranged to respond to said control unit and to said circuit under test and to transmit data therebetween; an insertable ROM memory arranged to be inserted into the circuit under test in place of the pre-existing ROM memory, said insertable ROM memory being programmed with instructions operable by the microprocessor of the circuit under test for testing the circuit under test and providing data output indicating the results of the test; and input means in said control unit and further comprising program means in said insertable ROM for causing the microprocessor in the circuit under test to: (a) read from said input means; (b) read and write data to selected ports in response to said input; (c) verify the data following said read and write operations; (d) transmit to said display means the results of said verification.
Claim 6
Dependent Claim
36 words
The electronic testing apparatus of claim 3 further comprising means to manually switch the circuit under test to maintain a wait state during a memory read operation and thereby hold address bits on the communication bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-14 | 1994-07-16 | 1995-01-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-14 | 1998-07-16 | 1999-01-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-14 | 2002-07-16 | 2003-01-15 | $7700.00 | Window Closed / Lapsed |