Semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit device comprising: a semiconductor chip having a main surface; a plurality of memory cells arranged along row and column directions on said main surface thereby forming rows and columns of memory cells, each of the memory cells being connected to corresponding word and data lines which extend in said column and row directions, respectively; a first wiring extending in said column direction for supplying a first potential to memory cells which are arranged in said column direction; and a second wiring extending in said column direction over said plurality of memory cells and comprising a different layer as that of said first wiring, said second wiring being applied with said first potential.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein said second wiring comprises an aluminum film.

Claim 4

A semiconductor integrated circuit device according to claim 2, wherein said data line comprises an aluminum film.

Claim 5

A semiconductor integrated circuit device according to claim 2, wherein said first wiring comprises a polycrystalline silicon film.

Claim 6

A semiconductor integrated circuit device according to claim 4, wherein each of said plurality of memory cells includes two driving transistors, two transfer transistors and two load elements.

Claim 7

A semiconductor integrated circuit device according to claim 5, wherein said two load elements are formed from said polycrystalline silicon film.

Claim 8

A semiconductor integrated circuit device according to claim 1, wherein said plurality of memory cells arranged in row and column directions compose a memory cell array, and said second wiring is connected to a power source wiring extending in said row direction at a portion out of the memory cell array.

Claim 9

A semiconductor integrated circuit device according to claim 7, wherein each of said power source wiring and second wiring comprises an aluminum film.

Claim 10

A semiconductor integrated circuit device comprising a semiconductor chip having a main surface; a plurality of memory cells arranged along row and column directions on said main surface thereby forming rows and columns of memory cells, each of one of said memory cells being connected to corresponding word and data lines which extend in said column and row directions, respectively, and each one of said memory cells including two driving transistors, two transfer transistors and two load elements; a first wiring extending in said column direction for supplying a first potential to memory cells arranged in said column direction, and said first wiring being connected to the two load elements of memory cells of respective columns of memory cells, a further word line extending in said column direction and connected to said word line; and a second wiring extending in said column direction over said plurality of memory cells and comprising a different layer as that of said first wiring, said second wiring being applied with said first potential.

Claim 11

A semiconductor integrated circuit device comprising a semiconductor chip having a main surface; a plurality of memory cells arranged along row and column directions on said main surface thereby forming rows and columns of memory cells, each of one of said memory cells being connected to corresponding word and data lines which extend in said column and row directions, respectively, and each one of said memory cells including two driving transistors, two transfer transistors and two load elements; a first wiring extending in said column direction for supplying a first potential to memory cells arranged in said column direction, and said first wiring being connected to the two load elements of memory cells of respective columns of memory cells, a further word line extending in said column direction and connected to said word line; and a second wiring extending in said column direction over said plurality of memory cells and comprising a different layer as that of said first wiring, said second wiring being applied with said first potential.

Claim 12

A semiconductor integrated circuit device according to claim 9, wherein said further word line and second wiring comprise a same layer of aluminum film.

Claim 13

A semiconductor integrated circuit device according to claim 10, wherein said further word line and second wiring extend in a parallel direction.

Claim 14

A semiconductor integrated circuit device according to claim 11, wherein said first wiring and said two load elements of each memory cell comprise a polycrystalline silicon film.

Claim 15

A semiconductor integrated circuit device according to claim 12, wherein one of said further word line and second wiring is formed over said first wiring.

Claim 16

A semiconductor integrated circuit device according to claim 13, wherein in each memory cell each one of said two driving transistors is series-connected with a respective one of said two load elements such that in each memory cell there is formed a flip-flop arrangement having a pair of logic inverters each one having inputs and outputs regeneratively cross-coupled and wherein each transfer transistor couples the output of one inverter and the input of the other of said pair of inverters in each memory cell to a corresponding data line.

Claim 17

A semiconductor integrated circuit device according to claim 14, wherein said chip is of an elongated rectangular shape having an outer periphery with a pair of short sides and a pair of long sides, and wherein said row and column directions extend in a direction parallel to the short and long sides of said chip, respectively.

Claim 18

A semiconductor integrated circuit device according to claim 9, wherein in each memory cell each one of said two driving transistors is series-connected with a respective one of said two load elements such that in each memory cell there is formed a flip-flop arrangement having a pair of logic inverters each one having inputs and outputs regeneratively cross-coupled and wherein each transfer transistor couples the output of one inverter and the input of the other of said pair of inverters in each memory cell to a corresponding data line.

Claim 19

A semiconductor integrated circuit device according to claim 16, wherein said chip is of an elongated rectangular shape having an outer periphery with a pair of short sides and a pair of long sides, and wherein said row and column directions extend in a direction parallel to the short and long sides of said chip, respectively.

Claim 20

A semiconductor integrated circuit device according to claim 5, wherein in each memory cell each one of said two driving transistors is series-connected with a respective one of said two load elements such that in each memory cell there is formed a flip-flop arrangement having a pair of logic inverters each one having inputs and outputs regeneratively cross-coupled and wherein each transfer transistor couples the output of one inverter and the input of the other of said pair of inverters in each memory cell to a corresponding data line.

Claim 21

A semiconductor integrated circuit device according to claim 18, wherein said chip is of an elongated rectangular shape having an outer periphery with a pair of short sides and a pair of long sides, and wherein said row and column directions extend in a direction parallel to the short and long sides of said chip, respectively.