US4982403A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrical circuit testing device and circuit comprising the said device
Assignee: Thales SA
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Filing: 1990-03-01
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Granted: 1991-01-01
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Expires: 2010-03-01
Abstract
Abstract A device for the testing of electrical circuits and a circuit comprising the said device are disclosed. The testing device is used to test electrical circuits by the generation of test vectors and the compression of the signal at the output of the device to be tested. The device of the present invention uses the same shift register, certain cells of which are looped at the input, by means of an exclusive-OR logic gate, to generate test vectors and perform signature analysis. Thus it is possible to test electrical circuits themselves as well as the input/output buses. The invention can be applied, in particular, to the testing of computers, microprocessors, memories, fast Fourier transform calculators, adders, multipliers, combinational logic systems or circuits including combinational logic systems or circuits that have internal memorizing devices.
Inventors
- 👤 Arnaud du Chene
- 👤 Bernard Dias
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:51
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/31813; G01R31/31816
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
111 words
A testing device for an electrical circuit device to be tested and especially, for digital and/or logical circuits to be tested, said testing device comprising: a shift register having a serial input and comprising a plurality of serially connected cells; means for connecting at least one of said cells to the input of said shift register; an external input/output bus to be connected to said device to be tested; multiplexer means for connecting said device to be tested to said input/output bus during normal operation of said device and for connecting said device to be tested to said shift register, without insulating said bus from said shift register, during testing operation.
Claim 2
Dependent Claim
111 words
A testing device for an electrical circuit device to be tested and especially, for digital and/or logical circuits to be tested, said testing device comprising: a shift register having a serial input and comprising a plurality of serially connected cells; means for connecting at least one of said cells to the input of said shift register; an external input/output bus to be connected to said device to be tested; multiplexer means for connecting said device to be tested to said input/output bus during normal operation of said device and for connecting said device to be tested to said shift register, without insulating said bus from said shift register, during testing operation.
Claim 3
Dependent Claim
41 words
A testing device according to claim 1 wherein only one cell is connected to said input of said shift register and wherein said connecting means comprise only a direct connection between said one cell and said input of said shift register.
Claim 4
Dependent Claim
31 words
A testing device according to claim 1, wherein at least two cells are connected to said input of said shift register and wherein said connecting means comprise an exclusive-OR logic gate.
Claim 5
Dependent Claim
30 words
A testing device according to claim 3, wherein the cells of said shift register, connected to the exclusive-OR logic gate inputs, correspond to the non-trivial exponents of a generating polynomial.
Claim 6
Dependent Claim
18 words
A testing device according to claim 1, further comprising a multiplexing controller device connected to said multiplexer means.
Claim 7
Dependent Claim
15 words
A testing device according to claim 1, wherein said testing device is a printed circuit.
Claim 8
Dependent Claim
15 words
A testing device according to claim 1, wherein said testing device is an integrated circuit.
Claim 9
Dependent Claim
15 words
A testing device according to claim 1, wherein said testing device comprises a combinational circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-31 | 1994-07-02 | 1995-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-31 | 1998-07-02 | 1999-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-31 | 2002-07-02 | 2003-01-01 | $7700.00 | Window Closed / Lapsed |