US4982268A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device package assembly hairing non-symmetrical semiconductor chip mounting within conductible lead pattern
Assignee: Texas Instruments Deutschland GmbH
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Filing: 1988-03-02
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Granted: 1991-01-01
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Expires: 2008-03-02
Abstract
Abstract A semiconductor device package assembly including a semiconductor chip (10) which contains an electronic circuit and is mounted on a support plate (12) of electrically conductive material. Disposed substantially in the plane of the support plate (12) are conductor strips (18) which extend in the direction towards the support plate (12) and at their ends remote from the support plate (12) are formed as terminal conductors (22) for establishing connections to external electronic circuits. Selected conductor strips (18) are connected to selected points of the electronic circuit in the chip (10). A housing is provided which encloses the support plate (12), the semiconductor chip (10) and the conductor strips (18) and out of which the terminal conductors (22) project. At least one of said terminal conductors (22) serves for the application of ground. The support plate (12) on which the semiconductor chip is mounted is arranged in non-symmetrical is offset relation with respect to the conductive lead pattern as defined by the conductor strips, being offset in the direction toward the at least one terminal conductor (22) serving for the application of ground and/or integrally connected to ground.
Inventors
- 👤 Josef Schuermann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 15:31
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W70/40; H10W70/421; H10W44/00; H10W44/501; H10W70/67; H10W70/69; H10W70/654; H10W70/655; H10W72/00; H10W72/50; H10W72/541; H10W72/5449; H10W72/851; H10W72/874; H10W72/884; H10W72/90; H10W72/931; H10W72/932; H10W90/00; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
263 words
A semiconductor device assembly comprising: a semiconductor chip having an electronic circuit provided thereon; a support plate of electrically conductive material on which said semiconductor chip is mounted; a conductive lead pattern at least substantially surrounding said support plate, said conductive lead pattern comprising a plurality of conductor strips disposed substantially in the plane of said support plate and being arranged about the perimeter of said support plate in outwardly extending relationship with respect thereto; the ends of said conductor strips remote from said support plate defining terminal conductors for establishing electrical connections to external electronic structures; means connecting selected conductor strips to selected points of said electronic circuit on said chip; at least one of said conductor strips providing a terminal conductor at its end remote from said support plate adapted to be connected to ground; said support plate being arranged in non-symmetrical offset geometrical relation with respect to a central location within said conductive lead pattern in the direction toward said terminal conductor adapted to be connected to ground such that the length of said at least one conductor strip providing said terminal conductor adapted to be connected to ground is relatively short in comparison to the lengths of other conductor strips located about a portion of the perimeter of said support plate other than that adjacent to said at least one conductor strip; and a housing enclosing said support plate, said semiconductor chip, and said plurality of conductor strips with the terminal conductors at the ends of said conductor strips remote from said support plate projecting outwardly of said housing.
Claim 2
Dependent Claim
263 words
A semiconductor device assembly comprising: a semiconductor chip having an electronic circuit provided thereon; a support plate of electrically conductive material on which said semiconductor chip is mounted; a conductive lead pattern at least substantially surrounding said support plate, said conductive lead pattern comprising a plurality of conductor strips disposed substantially in the plane of said support plate and being arranged about the perimeter of said support plate in outwardly extending relationship with respect thereto; the ends of said conductor strips remote from said support plate defining terminal conductors for establishing electrical connections to external electronic structures; means connecting selected conductor strips to selected points of said electronic circuit on said chip; at least one of said conductor strips providing a terminal conductor at its end remote from said support plate adapted to be connected to ground; said support plate being arranged in non-symmetrical offset geometrical relation with respect to a central location within said conductive lead pattern in the direction toward said terminal conductor adapted to be connected to ground such that the length of said at least one conductor strip providing said terminal conductor adapted to be connected to ground is relatively short in comparison to the lengths of other conductor strips located about a portion of the perimeter of said support plate other than that adjacent to said at least one conductor strip; and a housing enclosing said support plate, said semiconductor chip, and said plurality of conductor strips with the terminal conductors at the ends of said conductor strips remote from said support plate projecting outwardly of said housing.
Claim 3
Dependent Claim
34 words
A semiconductor device assembly as set forth in claim 1, wherein said at least one conductor strip providing said terminal conductor adapted to be connected to ground is integrally connected to said support plate.
Claim 4
Dependent Claim
189 words
A semiconductor device assembly as set forth in claim 2, wherein said housing has a rectangular configuration with longitudinal and transverse symmetry planes; said at least one conductor strip providing said terminal conductor adapted to be connected to ground being disposed in a region in proximity to be transverse symmetry plane of said housing; the remaining conductor strips and the terminal conductors corresponding thereto of said conductor lead pattern including conductor strips with terminal conductors serving for the application of input signal thereto and conductor strips with terminal conductors serving for the emission of output signals; said terminal conductors of said conductor strips serving for the application of input signals being arranged on one side of said transverse symmetry plane of said housing; said terminal conductors of said conductor strips serving to emit output signals being arranged on the other side of said transverse symmetry plane of said housing; and said support plate being arranged in non-symmetrical offset geometrical relation with respect to a central location within said conductive lead pattern in the direction toward the terminal conductors of said conductor strips serving for the emission of output signals.
Claim 5
Dependent Claim
40 words
A semiconductor device assembly as set forth in claim 3, wherein the conductor strips having the terminal conductors serving to emit output signals are wider than the conductor strips having the terminal conductors serving for the application of input signals.
Claim 6
Dependent Claim
44 words
A semiconductor device assembly as set forth in claim 4, further including shield conductor strips respectively disposed in the spaces between adjacent conductor strips having terminal conductors serving to emit output signals; and said shield conductor strips being integrally connected to said support plate.
Claim 7
Dependent Claim
113 words
A semiconductor device assembly as set forth in claim 3, wherein said semiconductor chip on said support plate includes a substrate of relatively low-resistance semiconductor material connected to said support plate in electrically conductive relationship; an epitaxial high-resistance semiconductor layer on said substrate; said electronic circuit being provided by said epitaxial semiconductor layer; a bond connection between said support plate and at least one ground connection point of said electronic circuit in said epitaxial layer; said epitaxial layer having a contact window provided therein communicating with said substrate; and said at least one ground connection point of said electronic circuit connecting said substrate to ground via the contact window in said epitaxial layer.
Claim 8
Dependent Claim
67 words
A semiconductor device assembly as set forth in claim 1, wherein said conductor strips disposed on opposite sides of at least one conductor strip having a terminal conductor serving for the application of an input signal thereto and the conductor strips disposed on opposite sides of at least one conductor strip having a terminal conductor serving to emit output signals are integrally connected to said support plate.
References Cited (Backward Citations)
US4023053A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-31 | 1994-07-02 | 1995-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-31 | 1998-07-02 | 1999-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-31 | 2002-07-02 | 2003-01-01 | $7700.00 | Window Closed / Lapsed |