US4980861A
Expired / Lapsed
US
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NAND stack ROM
Assignee: Microchip Technology Inc
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Filing: 1988-12-16
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Granted: 1990-12-25
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Expires: 2008-12-16
Abstract
Abstract Faster access time is achieved in a NAND stack ROM by eliminating depletion mode decode transistors, thus reducing column capacitance. Horizontal ground straps of diffusion are eliminated to reduce chip area by running virtual ground lines vertically through the array. Adjacent columns are tied to alternating sense amplifiers utilizing a simple multiplexer connected to the virtual ground lines.
Inventors
- 👤 Christian E. Herdt
- 👤 Steven H. Cliadakis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:07
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C17/123
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
171 words
A NAND Stack ROM array formed in a substrate comprising first and second substantially parallel, spaced columns of series connected bit switching means formed in said substrate, each of said columns comprising a stack of said bit switching means, a first node at one end of said stack, a second node at the other end of said stack and stack decode means wherein said stack decode means comprises a single enhancement mode transistor interposed between said stack and said first node, means for precharging said first node, first and second sense amplifiers, means, effective when actuated, for operably connecting said first node of a selected column with one of said first and second sense amplifiers and means for generating and applying a virtual ground signal to said connecting means associated with said selected column to actuate same and to said second node of said selected column, said signal applying means comprising a conductive region in said substrate extending between and in the same general direction in said substrate as said columns.
Claim 2
Dependent Claim
171 words
A NAND Stack ROM array formed in a substrate comprising first and second substantially parallel, spaced columns of series connected bit switching means formed in said substrate, each of said columns comprising a stack of said bit switching means, a first node at one end of said stack, a second node at the other end of said stack and stack decode means wherein said stack decode means comprises a single enhancement mode transistor interposed between said stack and said first node, means for precharging said first node, first and second sense amplifiers, means, effective when actuated, for operably connecting said first node of a selected column with one of said first and second sense amplifiers and means for generating and applying a virtual ground signal to said connecting means associated with said selected column to actuate same and to said second node of said selected column, said signal applying means comprising a conductive region in said substrate extending between and in the same general direction in said substrate as said columns.
Claim 3
Dependent Claim
14 words
The ROM of claim 1 wherein each of said columns comprises colinearly aligned stacks.
Claim 4
Dependent Claim
14 words
The ROM of claim 2 wherein said second node is interposed between said stacks.
Claim 5
Dependent Claim
18 words
The ROM of claim 2 wherein said first node comprises end nodes at each end of said column.
References Cited (Backward Citations)
US4636664A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-24 | 1994-06-25 | 1994-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-24 | 1998-06-25 | 1998-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-24 | 2002-06-25 | 2002-12-25 | $7700.00 | Window Closed / Lapsed |