State metric memory arrangement for a viterbi decoder

Claim 2

A state metric memory arrangement for a VITERBI decoder comprising: register means for storing a plurality of state metrics, said register means operating to serially shift each of said plurality of state metrics a predefined number of times; serial to parallel means connected to said register means, said serial to parallel means operating to form required pairs of said state metrics; add-compare-select means connected to said serial to parallel means and to said register means, said add-compare-select means operating to calculate new state metrics and operating to transmit said new state metrics to said register means in a particular order for storage; and said register means further operating to store certain ones of said new state metrics interleaved with others of said new state metrics.

Claim 3

A state metric memory arrangement as claimed in claim 1, wherein there is further included control means connected to said register means, said control means operating to control said interleaved storing of said register means.

Claim 4

A state metric memory arrangement as claimed in claim 2, said register means including a first plurality of register unit means, including at least a first and a last register unit means, said first plurality of register unit means being serially connected, each of said first plurality of register unit means connected to and operating in response to said control means to sequentially shift said state metrics, and said first plurality of register unit means further operating in response to said control means to inhibit said sequential shifting, and a particular one of said first plurality of register unit means operating in response to said control means to directly insert a particular state metric from said add-compare-select means into said particular register unit means.

Claim 5

A state metric memory arrangement as claimed in claim 3, said register means further including a second plurality of register unit means, including at least a first and last register unit means, said second plurality of register unit means being serially connected, said first register unit means of said second plurality being serially connected to said last register unit means of said first plurality and said last register unit means of said second plurality being connected to said serial to parallel means, said second plurality of register unit means operating to sequentially shift said new state metrics of said last register unit means of said first plurality to said serial to parallel means.

Claim 6

A state metric memory arrangement as claimed in claim 4, said connection of said add-compare-select means to each of first plurality of register unit means including a bus connection for parallel loading of said state metrics into selected ones of said first plurality of register unit means.

Claim 7

A state metric memory arrangement as claimed in claim 5, said connection of said control means to each of said first plurality of register means including a bus connection.

Claim 8

A state metric memory arrangement for a VITERBI decoder comprising: state counter means for generating a series of states indicating which of said state metrics are required for processing; address generation means connected to said state counter means and operating to produce a physical address of retrieving said required state metrics; memory means connected to said state counter means and to said address generation means, said memory means for storing said state metrics, said memory means operating in response to said state counter means and to said physical address of said address generation means to retrieve previously stored state metrics; said address generation means including shifting means connected to said memory means and coupled to said state counter means, said shifting means operating in response to said state counter means to transform said state of said state counter means to an address for accessing said memory means for retrieving said stored state metrics and for storing said pairs of said new state metrics; said shifting means including barrel shifting means; state metric calculation means connected to said memory means, said state metric calculation means operating in response to said retrieved state metrics to calculate new state metrics; and said memory means further operating in response to said address generation means and to said state metric calculation means to store said new state metrics at a location from which said required state metrics were retrieved.

Claim 9

A state metric memory arrangement for a VITERBI decoder comprising: state counter means for generating a series of states indicating which of said state metrics are required for processing; address generation means connected to said state counter means and operating to produce a physical address of retrieving said required state metrics; memory means connected to said state counter means and to said address generation means, said memory means for storing said state metrics, said memory means operating in response to said state counter means and to said physical address of said address generation means to retrieve previously stored state metrics; said address generation means including shifting means connected to said memory means and coupled to said state counter means, said shifting means operating in response to said state counter means to transform said state of said state counter means to an address for accessing said memory means for retrieving said stored state metrics and for storing said pairs of said new state metrics; said shifting means including barrel shifting means; state metric calculation means connected to said memory means, said state metric calculation means operating in response to said retrieved state metrics to calculate new state metrics; and said memory means further operating in response to said address generation means and to said state metric calculation means to store said new state metrics at a location from which said required state metrics were retrieved.

Claim 10

A state metric memory arrangement as claimed in claim 7, said state metric calculation means including: regrouping means connected to said memory means, said regrouping means operating to receive a plurality of said state metrics and operating to order said received state metrics so that regrouped state metrics are simultaneously presented for calculation; and add-compare-select means connected to said regrouping means, said add-compare-select means operating to calculate said new state metrics from said regrouped state metrics.

Claim 11

A state metric memory arrangement as claimed in claim 8, said state metric calculation means further including: serial to parallel means connected to said add-compare-select means, said serial to parallel means operating to produce pairs of said new state metrics; said memory means operating in response to said address generation means to store said pairs of new state metrics. add-compare-select means connected to said regrouping means, said add-compare-select means operating to calculate said new state metrics from said regrouped state metrics.

Claim 12

A state metric memory arrangement as claimed in claim 9, said address generation means further including adjusting means connected between said shifting means and said state counter means, said adjusting means operating to subtract a predetermined number from said state indicating a time delay for retrieving and storing said state metrics from said memory means.

Claim 13

A state metric memory arrangement as claimed in claim 10, said address generation means further including shift counter means connected between said state counter means and said shifting means, said shift counter means operating to control said shifting means to shift said state of said state counter to form an address for accessing said state metric memory.

Claim 14

A state metric memory arrangement as claimed in claim 11, said state metric memory including a random access memory (RAM).

Claim 15

A state metric memory arrangement as claimed in claim 11, said state counter means further connected to said state metric memory of transmitting a read/write signal to said state metric memory.

Claim 16

A state metric memory arrangement for a VITERBI decoder comprising: register means for storing a plurality of state metrics, said register means operating to serially shift each of said plurality of state metrics a predefined number of times; state metric calculation means connected to said register means, said state metric calculation means operating upon required pairs of state metrics to produce new state metrics in a particular order for storage; and said register means further operating to store certain ones of said new state metrics interleaved with others of said new state metrics.

Claim 17

A state metric memory arrangement for a VITERBI decoder comprising: register means for storing a plurality of state metrics, said register means operating to serially shift each of said plurality of state metrics a predefined number of times; state metric calculation means connected to said register means, said state metric calculation means operating upon required pairs of state metrics to produce new state metrics in a particular order for storage; and said register means further operating to store certain ones of said new state metrics interleaved with others of said new state metrics.