US4979172A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microcomputer
Assignee: Toshiba Corp
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Filing: 1988-12-27
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Granted: 1990-12-18
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Expires: 2008-12-27
Abstract
Abstract A microcomputer incorporates an EPROM for storing programs and data which a CPU executes, and includes, as operating modes, a microcomputer mode for operating as a microcomputer, a test mode for testing the operation of the CPU and an EPROM mode for writing in and reading from the EPROM. A test terminal of the microcomputer is used for mode switching control, i.e., used as a power supply testing/programming terminal. By the logic level of this terminal, switching between the microcomputer mode and the test mode is performed, and a programming voltage is also supplied. By a control terminal, which is another terminal, switching between the test mode and the EPROM mode is performed.
Inventors
- 👤 Kazuyuki Murase
- 👤 Naoyasu Tasaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:10
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G11; G11C; G11C5/00; G11C5/06; G11C5/066; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31701; G06F15/00; G06F15/76; G06F15/78; G06F15/7807; G06F15/7814
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
171 words
An apparatus comprising: a microcomputer with at least an MCU terminal, a TEST terminal and an EPROM terminal, said microcomputer capable of operating in at least a microcomputer mode activated by an MCU signal input to said MCU terminal, a test mode activated by a TEST signal input to said TEST terminal and an EPROM mode activated by an EPROM signal input to said EPROM terminal; and power supply testing/programming means for receiving a testing/programming signal and a control signal, and for outputting said MCU, TEST and EPROM signals, said MCU signal indicating said microcomputer mode whenever said control signal is in a first logic level and said testing/programming signal is in a first logic state, said TEST signal indicating said test mode whenever said control signal is in a second logic level and said testing/programming signal is in a second logic state, and said EPROM signal indicating said EPROM mode whenever said control signal is in a first logic state and said testing/programming signal is in a first logic state.
Claim 2
Independent Claim
171 words
An apparatus comprising: a microcomputer with at least an MCU terminal, a TEST terminal and an EPROM terminal, said microcomputer capable of operating in at least a microcomputer mode activated by an MCU signal input to said MCU terminal, a test mode activated by a TEST signal input to said TEST terminal and an EPROM mode activated by an EPROM signal input to said EPROM terminal; and power supply testing/programming means for receiving a testing/programming signal and a control signal, and for outputting said MCU, TEST and EPROM signals, said MCU signal indicating said microcomputer mode whenever said control signal is in a first logic level and said testing/programming signal is in a first logic state, said TEST signal indicating said test mode whenever said control signal is in a second logic level and said testing/programming signal is in a second logic state, and said EPROM signal indicating said EPROM mode whenever said control signal is in a first logic state and said testing/programming signal is in a first logic state.
Claim 3
Dependent Claim
95 words
An apparatus as claimed in claim 1, wherein said power supply testing/programming means further comprises: inverting means for inverting said testing/programming signal and outputting said MCU signal; a flip-flop means for receiving said testing/programming signal and said control signal and for generating a positive logic output and a negative logic output corresponding to said control signal; first AND gate means for receiving said positive and negative logic outputs and for outputting said TEST signal; and second AND gate means for receiving said negative logic output and said testing/programming signal and for outputting said EPROM signal.
Claim 4
Dependent Claim
28 words
An apparatus as claimed in claim 1, wherein said power supply testing/programming means receives a voltage for programming said microcomputer while said microcomputer operates in said EPROM mode.
References Cited (Backward Citations)
US4317199A
Cited
US4433413A
Cited
US4468768A
Cited
US4641308A
Cited
US4622668A
Cited
US4811345A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-17 | 1994-06-18 | 1994-12-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-17 | 1998-06-18 | 1998-12-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-17 | 2002-06-18 | 2002-12-18 | $7700.00 | Window Closed / Lapsed |