Sampled-value code processing device

Claim 2

A sampled-value code processing device comprising: (a) input means for inputting a sampled-value code series representing sampled values of an information signal at a predetermined period; (b) code series converting means for forming, from the sampled-value code series input by said input means, a first code series consisting of codes related to a group of sampled values determined according to a predetermined rule and a second code series consisting of codes related to sampled values other than the group of sampled values, and for outputting the first code series and the second code series at an output period longer than the predetermined period, said converting means including a parallelizing circuit for outputting a plurality of code series by parallelizing a plurality of codes in the sampled-value code series; and (c) filtering means for applying a filtering process to the first code series output from said converting means by using said second code series.

Claim 3

A device according to claim 1, wherein said parallelizing circuit outputs adjacent two codes in the sampled-value code series in parallel at the same timing.

Claim 4

A device according to claim 1, wherein said parallelizing circuit outputs the plurality of code series at a period equal to the output period of said code series converting means.

Claim 5

A device according to claim 1, wherein said information signal is a video signal, and wherein said filtering means includes a delay circuit having a delay time equal to integer times a period corresponding to one line of the video signal, and a computing circuit for computing a code series to be input to said delay circuit and a code series output from said delay circuit.

Claim 6

A device according to claim 1, wherein said filtering means includes a delay circuit having a delay time corresponding to the output period of said code series converting means, and a computing circuit for computing a code series to be input to said delay circuit and a code series output from said delay circuit.

Claim 7

A device according to claim 5, wherein said filtering means includes a first processing circuit to which only the second code series is input, and a computing circuit for computing a code series output from said first processing circuit and the first code series to output a third code series.

Claim 8

A device according to claim 1, wherein said code series converting means further includes a switching circuit for selectively outputting the plurality of code series output from said parallelizing circuit to form the first code series and the second code series.

Claim 9

A device according to claim 7, wherein the information signal is a video signal, and wherein said switching circuit is changed over in each period corresponding to one line of the video signal.

Claim 10

A device according to claim 8, wherein said switching circuit includes a first switch for outputting the first code series and a second switch for outputting the second code series, said first switch and said second switch outputting codes of respective different code series in the plurality of code series.

Claim 11

A sampled-value code processing device comprising: (a) input means for inputting a sampled-value code series representing sampled values of an information signal at a predetermined period; (b) code series converting means for forming, from the sampled-value code series input by said input means, a first code series consisting of codes related to a group of sampled values determined according to a predetermined rule, and for outputting the first code series at an output period longer than the predetermined period, said converting means including a parallelizing circuit for outputting a plurality of code series, by parallelizing a plurality of codes in the sample-value code series; and (c) filtering means for applying a filtering process to the first code series output from said converting means by using codes related to sampled values other than the group of sampled values.

Claim 12

A sampled-value code processing device comprising: (a) input means for inputting a sampled-value code series representing sampled values of an information signal at a predetermined period; (b) code series converting means for forming, from the sampled-value code series input by said input means, a first code series consisting of codes related to a group of sampled values determined according to a predetermined rule, and for outputting the first code series at an output period longer than the predetermined period, said converting means including a parallelizing circuit for outputting a plurality of code series, by parallelizing a plurality of codes in the sample-value code series; and (c) filtering means for applying a filtering process to the first code series output from said converting means by using codes related to sampled values other than the group of sampled values.

Claim 13

A sampled-value code processing device comprising: (a) input means for inputting a sampled-value code series representing sampled values of an information signal at a predetermined period; (b) code series converting means for forming, from the sample-value code series input by said input means, a first code series consisting of codes related to a group of sampled values determined according a predetermined rule and a second code series consisting of codes related to sampled values other than the group of sampled values, and for synchronously outputting the first code series and the second code series at an output period longer that the predetermined period, said converting means including a parallelizing circuit for outputting a plurality of code series by parallelizing a plurality of codes in the sampled-value code series; and (c) filtering means for applying a filtering process to the first code series output from said converting means by using codes related to sampled values other than the group of sampled values.

Claim 14

A sampled-value code processing device comprising: (a) input means for inputting a sampled-value code series representing sampled values of an information signal at a predetermined period; (b) code series converting means for forming, from the sample-value code series input by said input means, a first code series consisting of codes related to a group of sampled values determined according a predetermined rule and a second code series consisting of codes related to sampled values other than the group of sampled values, and for synchronously outputting the first code series and the second code series at an output period longer that the predetermined period, said converting means including a parallelizing circuit for outputting a plurality of code series by parallelizing a plurality of codes in the sampled-value code series; and (c) filtering means for applying a filtering process to the first code series output from said converting means by using codes related to sampled values other than the group of sampled values.