Abstract A transistor (14) having a plurality of sub-transistors (26a-f) includes a voltage controlling device (45). The voltage controlling device induces a current through an elongated gate (24) producing a voltage drop across the elongated gate (24) by providing a path between one end of the gate and ground (32). The voltage drop across the elongated gate (24) sequentially reduces the gate voltage present at each of the sub-transistors (29a-f), thereby reducing the amount of current which the sub-transistors (29a-f) can conduct. The voltage controlling circuit (45) gradually reduces the current through the elongated gate (24), thereby increasing the amount of current through the sub-transistors (29a-f). The time interval over which the conductive device induces a current through the elongated gate (24) can be adjusted by positioning the connection to the gate of a transistor (62) along the elongated gate (24). The limiting of current through the output sub-transistors (29a-f) for a predetermined time interval reduces the generation of output noise by controlling the rate at which current is changing in that output.
A transistor circuit comprising: a substrate including semiconductor surface areas; a plurality of N-channel sub-transistors formed in said surface areas, said transistors including a shared gate; a plurality of P-channel sub-transistors formed in said surface areas, said P-channel sub-transistors including a shared gate, each of said P-channel sub-transistors being connected to an associated N-channel sub-transistor at a common drain connection, each P-channel sub-transistor being operable in complementary fashion with its associated N-channel sub-transistor; each said shared gate having a predetermined resistance and being disposed in said semiconductor surface areas such that a gate signal applied to a first end region of said gate propagates along the length of said gate in a predetermined time interval, the propagation of said gate signal along said shared gate causing graduated turn-on of said sub-transistors; a conducting device connected to a second end of each said shared gate to allow a transient current to pass from said first end region of said shared gate through said conducting device to cause a voltage drop across said shared gate, said voltage drop reducing the amount of current conducted by said sub-transistors; and a switching device connected to said conducting device and each said shared gate, said switching device operable to inhibit current through said shared gate a predetermined time after sensing a signal on said shared gate.
Claim 2
Dependent Claim
221 words
A transistor circuit comprising: a substrate including semiconductor surface areas; a plurality of N-channel sub-transistors formed in said surface areas, said transistors including a shared gate; a plurality of P-channel sub-transistors formed in said surface areas, said P-channel sub-transistors including a shared gate, each of said P-channel sub-transistors being connected to an associated N-channel sub-transistor at a common drain connection, each P-channel sub-transistor being operable in complementary fashion with its associated N-channel sub-transistor; each said shared gate having a predetermined resistance and being disposed in said semiconductor surface areas such that a gate signal applied to a first end region of said gate propagates along the length of said gate in a predetermined time interval, the propagation of said gate signal along said shared gate causing graduated turn-on of said sub-transistors; a conducting device connected to a second end of each said shared gate to allow a transient current to pass from said first end region of said shared gate through said conducting device to cause a voltage drop across said shared gate, said voltage drop reducing the amount of current conducted by said sub-transistors; and a switching device connected to said conducting device and each said shared gate, said switching device operable to inhibit current through said shared gate a predetermined time after sensing a signal on said shared gate.
Claim 3
Dependent Claim
44 words
A transistor circuit as recited in claim 1, wherein said conducting device comprises a plurality of voltage pull-up devices connected to the shared gate of said P-channel sub-transistors and a plurality of voltage pull-down devices connected to the shared gate of said N-channel sub-transistors.
Claim 4
Dependent Claim
27 words
A transistor circuit as recited in claim 2, wherein each said pull-up device comprises a P-channel transistor and wherein each said pull-down device comprises a N-channel transistor.