High speed bipolar-MOS logic circuit including a series coupled arrangement of a bipolar transistor and a logic block having a MOSFET

Claim 2

A logic circuit comprising: first and second power supply terminals for receiving first and second supply voltages; an output terminal; at least one input terminal for receiving an input signal; load means coupled between said first power supply terminal and said output terminal; a first bipolar transistor coupled to have a collector coupled to said output terminal, a base coupled to be supplied with a predetermined voltage, and an emitter; and a first MOSFET coupled to have a source-drain path coupled between the emitter of said bipolar transistor and said second power supply terminal, and a gate coupled to said input terminal, wherein a plurality of said input terminals are provided, and wherein said logic circuit further comprises: a second MOSFET coupled to have a source-drain path coupled between the source-drain path of said first MOSFET and said second power supply terminal, and a gate coupled to receive an input signal to be supplied to the input terminal different from that coupled to the date of said first MOSFET.

Claim 3

A logic circuit comprising: first and second power supply terminals for receiving first and second supply voltages; an output terminal; at least one input terminal for receiving an input signal; load means coupled between said first power supply terminal and said output terminal; a first bipolar transistor coupled to have a collector coupled to said output terminal, a base coupled to be supplied with a predetermined voltage, and an emitter; and a first MOSFET coupled to have source-drain path coupled between the emitter of said bipolar transistor and said second power supply terminal, and a gate coupled to said input terminal, wherein a plurality of said input terminals are provided, and wherein said logic circuit further comprises: a second MOSFET coupled to have a source-drain path coupled between the emitter of said first bipolar transistor and said second power supply terminal, and a gate coupled to receive an input signal to be supplied to the input terminal different from that coupled to the gate of said first MOSFET.

Claim 4

A logic circuit comprising: first and second power supply terminals for receiving first and second supply voltages; an output terminal; at least one input terminal for receiving an input signal; load means coupled between said first power supply terminal and said output terminal; a first bipolar transistor coupled to have a collector coupled to said output terminal, a base coupled to be supplied with a predetermined voltage, and an emitter; and a first MOSFET coupled to have source-drain path coupled between the emitter of said bipolar transistor and said second power supply terminal, and a gate coupled to said input terminal, wherein a plurality of said input terminals are provided, and wherein said logic circuit further comprises: a second MOSFET coupled to have a source-drain path coupled between the emitter of said first bipolar transistor and said second power supply terminal, and a gate coupled to receive an input signal to be supplied to the input terminal different from that coupled to the gate of said first MOSFET.

Claim 5

A logic circuit according to claim 2, further comprising: diode means coupled between said first power supply terminal and said output terminal to prevent said first bipolar transistor from operating in an unsaturation region.

Claim 6

A logic circuit comprising: first and second power supply terminals for receiving first and second supply voltages; an output terminal; at least one input terminal for receiving an input signal; load means coupled between said first power supply terminal and said output terminal; a first bipolar transistor coupled to have a collector coupled to said output terminal, a base coupled to be supplied with a predetermined voltage, and an emitter; a first MOSFET coupled to have a source-drain path coupled between the emitter of said bipolar transistor and said second power supply terminal, and a gate coupled to said input terminal; a second bipolar transistor coupled to have an emitter-collector path coupled between said first power supply terminal and said output, and a base coupled to said output terminal, further comprising: current source means coupled between said output and said second power supply terminal.

Claim 7

A logic circuit comprising: first and second power supply terminals for receiving first and second supply voltages; an output terminal; at least one input terminal for receiving an input signal; load means coupled between said first power supply terminal and said output terminal; a first bipolar transistor coupled to have a collector coupled to said output terminal, a base coupled to be supplied with a predetermined voltage, and an emitter; a first MOSFET coupled to have a source-drain path coupled between the emitter of said bipolar transistor and said second power supply terminal, and a gate coupled to said input terminal; a second bipolar transistor coupled to have an emitter-collector path coupled between said first power supply terminal and said output, and a base coupled to said output terminal, further comprising: current source means coupled between said output and said second power supply terminal.

Claim 8

A logic circuit comprising: first and second power supply terminals for receiving first and second supply voltages; an output terminal; at least one input terminal for receiving an input signal; load means coupled between said first power supply terminal and said output terminal; a first bipolar transistor coupled to have a collector coupled to said output terminal, a base coupled to be supplied with a predetermined voltage, and an emitter; a first MOSFET coupled to have a source-drain path coupled between the emitter of said bipolar transistor and said second power supply terminal, and a gate coupled to said input terminal; an output; and a second bipolar transistor coupled to have an emitter-collector path coupled between said first power supply terminal and said output, and a base coupled to said output terminal, further comprising: an output MOSFET coupled to have a source-drain path coupled between said output and said second power supply terminal, and a gate coupled to the base of said second bipolar transistor, wherein said second bipolar transistor and said output MOSFET are complementarily operated to one another.

Claim 9

A logic circuit comprising: first and second power supply terminals for receiving first and second supply voltages; an output terminal; at least one input terminal for receiving an input signal; load means coupled between said first power supply terminal and said output terminal; a first bipolar transistor coupled to have a collector coupled to said output terminal, a base coupled to be supplied with a predetermined voltage, and an emitter; a first MOSFET coupled to have a source-drain path coupled between the emitter of said bipolar transistor and said second power supply terminal, and a gate coupled to said input terminal; an output; and a second bipolar transistor coupled to have an emitter-collector path coupled between said first power supply terminal and said output, and a base coupled to said output terminal, further comprising: an output MOSFET coupled to have a source-drain path coupled between said output and said second power supply terminal, and a gate coupled to the base of said second bipolar transistor, wherein said second bipolar transistor and said output MOSFET are complementarily operated to one another.

Claim 10

A logic circuit comprising: first and second power supply terminals for receiving first and second supply voltages; an output terminal; at least one input terminal for receiving an input signal; load means coupled between said first power supply terminal and said output terminal; a first bipolar transistor coupled to have a collector coupled to said output terminal, a base coupled to be supplied with a predetermined voltage, and an emitter; and a first MOSFET coupled to have a source-drain path coupled between the emitter of said bipolar transistor and said second power supply terminal, and a gate coupled to said input terminal, further comprising: an output circuit for receiving an output signal on said output terminal and executing charging and discharging of an output capacitance of said output circuit in response to said received output signal.

Claim 11

A logic circuit comprising: first and second power supply terminals for receiving first and second supply voltages; an output terminal; at least one input terminal for receiving an input signal; load means coupled between said first power supply terminal and said output terminal; a first bipolar transistor coupled to have a collector coupled to said output terminal, a base coupled to be supplied with a predetermined voltage, and an emitter; and a first MOSFET coupled to have a source-drain path coupled between the emitter of said bipolar transistor and said second power supply terminal, and a gate coupled to said input terminal, further comprising: an output circuit for receiving an output signal on said output terminal and executing charging and discharging of an output capacitance of said output circuit in response to said received output signal.

Claim 12

A logic circuit comprising: first and second power supply terminals for receiving first and second supply voltages; an output terminal; at least one input terminal for receiving an input signal; load means coupled between said first power supply terminal and said output terminal; a first bipolar transistor coupled to have a collector coupled to said output terminal, a base coupled to be supplied with a predetermined voltage, and an emitter; and a first MOSFET coupled to have a source-drain path coupled between the emitter of said bipolar transistor and said second power supply terminal, and a gate coupled to said input terminal, further comprising: wherein a plurality of said input terminals are provided, and wherein said logic circuit further comprises: a bipolar transistor coupled to have an emitter-collector path coupled between said first power supply terminal and the emitter of said first bipolar transistor, and a base coupled to receive an input signal to be supplied from the input terminal different from that coupled to the gate of said first MOSFET.

Claim 13

A logic circuit comprising: first and second power supply terminals for receiving first and second supply voltages; an output terminal; at least one input terminal for receiving an input signal; load means coupled between said first power supply terminal and said output terminal; a first bipolar transistor coupled to have a collector coupled to said output terminal, a base coupled to be supplied with a predetermined voltage, and an emitter; and a first MOSFET coupled to have a source-drain path coupled between the emitter of said bipolar transistor and said second power supply terminal, and a gate coupled to said input terminal, further comprising: wherein a plurality of said input terminals are provided, and wherein said logic circuit further comprises: a bipolar transistor coupled to have an emitter-collector path coupled between said first power supply terminal and the emitter of said first bipolar transistor, and a base coupled to receive an input signal to be supplied from the input terminal different from that coupled to the gate of said first MOSFET.

Claim 14

A semiconductor integrated circuit device comprising: a logic circuit for receiving input signals at its input terminals to produce an output signal of ECL level at its output terminal, said logic circuit including: load means for converting a current signal into a voltage signal according to said current signal, said load means being coupled between said output terminal and a first power supply terminal to be supplied with a first power supply voltage of said circuit device; a first bipolar transistor having a base coupled to receive a predetermined voltage, a collector coupled to said output terminal, and an emitter; and a plurality of MOSFETs having gates coupled to receive said input signals, respectively, and source-drain paths coupled between the emitter of said first bipolar transistor and a second power supply terminal to be supplied with a second power supply voltage of said circuit device, said first power supply voltage being higher than said second power supply voltage.

Claim 15

A semiconductor integrated circuit device comprising: a logic circuit for receiving input signals at its input terminals to produce an output signal of ECL level at its output terminal, said logic circuit including: load means for converting a current signal into a voltage signal according to said current signal, said load means being coupled between said output terminal and a first power supply terminal to be supplied with a first power supply voltage of said circuit device; a first bipolar transistor having a base coupled to receive a predetermined voltage, a collector coupled to said output terminal, and an emitter; and a plurality of MOSFETs having gates coupled to receive said input signals, respectively, and source-drain paths coupled between the emitter of said first bipolar transistor and a second power supply terminal to be supplied with a second power supply voltage of said circuit device, said first power supply voltage being higher than said second power supply voltage.

Claim 16

A semiconductor integrated circuit device according to claim 8, wherein said first bipolar transistor is of an NPN type, and wherein said plurality of MOSFETs are of an N-channel type.

Claim 17

A semiconductor integrated circuit device according to claim 8, wherein the source-drain paths of said plurality of MOSFETs are coupled in series between the emitter of said first bipolar transistor and said second power supply terminal.

Claim 18

A semiconductor integrated circuit device according to claim 8, wherein the source-drain paths of said plurality of MOSFETs are coupled in parallel between the emitter of said first bipolar transistor and said second power supply terminal.

Claim 19

A semiconductor integrated circuit device according to claim 8, further comprising: a second bipolar transistor coupled to have a base coupled to said output terminal, a collector coupled to said first power supply terminal, and an emitter for producing an output.

Claim 20

A semiconductor integrated circuit device comprising: a plurality of logic circuits coupled to one another each for receiving input signals at its input terminals each to produce an output signal of ECL level at its output terminal, each of said logic circuits including: load means for converting a current signal into a voltage signal according to said current signal, said load means being coupled between said output terminal and a first power supply terminal to be supplied with a first power supply voltage of said circuit device; a first bipolar transistor having a base coupled to receive a predetermined voltage, a collector coupled to said output terminal, and an emitter; and a plurality of MOSFET having gates coupled to receive said input signals, respectively, and source-drain paths coupled between the emitter of said first bipolar transistor and a second power supply terminal to be supplied with a second power supply voltage of said circuit device, said first power supply voltage being higher than said second power supply voltage.

Claim 21

A semiconductor integrated circuit device comprising: a plurality of logic circuits coupled to one another each for receiving input signals at its input terminals each to produce an output signal of ECL level at its output terminal, each of said logic circuits including: load means for converting a current signal into a voltage signal according to said current signal, said load means being coupled between said output terminal and a first power supply terminal to be supplied with a first power supply voltage of said circuit device; a first bipolar transistor having a base coupled to receive a predetermined voltage, a collector coupled to said output terminal, and an emitter; and a plurality of MOSFET having gates coupled to receive said input signals, respectively, and source-drain paths coupled between the emitter of said first bipolar transistor and a second power supply terminal to be supplied with a second power supply voltage of said circuit device, said first power supply voltage being higher than said second power supply voltage.

Claim 22

A semiconductor integrated circuit device according to claim 13, wherein said first bipolar transistor is of an NPN type, and wherein said plurality of MOSFETs are of an N-channel type.

Claim 23

A semiconductor integrated circuit device according to claim 13, wherein said source-drain paths of said plurality of MOSFETs are coupled in series between the emitter of said first bipolar transistor and said second power supply terminal.

Claim 24

A semiconductor integrated circuit device according to claim 13, wherein said source-drain paths of said plurality of MOSFETs are coupled in parallel between the emitter of said first bipolar transistor and said second power supply terminal.

Claim 25

A semiconductor integrated circuit device according to claim 13, further comprising: a second bipolar transistor coupled to have a base coupled to said output terminal, a collector coupled to said first power supply terminal, and an emitter for producing an output.

Claim 26

A semiconductor integrated circuit device comprising: first and second power supply terminals for receiving first and second supply voltages, respectively; an output terminal; an output bipolar transistor having an emitter-collector path coupled between the first supply voltage terminal and the output terminal, and a base, the output bipolar transistor executing one of charging and discharging of a capacitance associated with the output terminal in response to a base driving signal supplied to the base thereof; means coupled between the output terminal and the second supply voltage terminal for executing the other of the charging and discharging of the capacitance; a load circuit coupled between the first supply voltage terminal and the base of the output bipolar transistor; a first bipolar transistor having a collector coupled to the base of the output bipolar transistor, a base coupled to receive a first input, and an emitter; and a first MOSFET having a source-drain path coupled between the emitter of the first bipolar transistor and the second supply voltage terminal, and a gate coupled to receive a second input.

Claim 27

A semiconductor integrated circuit device comprising: first and second power supply terminals for receiving first and second supply voltages, respectively; an output terminal; an output bipolar transistor having an emitter-collector path coupled between the first supply voltage terminal and the output terminal, and a base, the output bipolar transistor executing one of charging and discharging of a capacitance associated with the output terminal in response to a base driving signal supplied to the base thereof; means coupled between the output terminal and the second supply voltage terminal for executing the other of the charging and discharging of the capacitance; a load circuit coupled between the first supply voltage terminal and the base of the output bipolar transistor; a first bipolar transistor having a collector coupled to the base of the output bipolar transistor, a base coupled to receive a first input, and an emitter; and a first MOSFET having a source-drain path coupled between the emitter of the first bipolar transistor and the second supply voltage terminal, and a gate coupled to receive a second input.

Claim 28

The circuit device of claim 18, wherein the means includes an output MOSFET having a source-drain path coupled between the output terminal and the second supply voltage terminal, and wherein the output MOSFET is turned on when the output bipolar transistor is turned off.

Claim 29

The circuit device of claim 19, wherein the output MOSFET has a gate coupled to the base of the output bipolar transistor.

Claim 30

The circuit device of claim 20, wherein the output bipolar transistor is of an NPN type, and wherein the output MOSFET is of a P-channel type.

Claim 31

The circuit device of claim 19, wherein the load circuit includes a resistance element coupled between the first supply voltage terminal and the base of the output bipolar transistor.

Claim 32

The circuit device of claim 22, wherein the load circuit further includes a level clamping element coupled between the first supply voltage terminal and the base of the output bipolar transistor.

Claim 33

The circuit device of claim 23, wherein a voltage difference between the first and second voltages is equal to or lower than 3.3 volt.

Claim 34

The circuit device of claim 24, wherein said circuit device provides an output signal at the output terminal of an ECL level.

Claim 35

The circuit device of claim 18, wherein the output and first bipolar transistors are of an NPN-type, and the first MOSFET is of an N-channel type.

Claim 36

The circuit device of claim 26, wherein a voltage difference between the first and second voltages is equal to or lower than 3.3 volt.

Claim 37

The circuit device of claim 18, further comprising: a second MOSFET having a source-drain path coupled between the source-drain path of the first MOSFET and the second supply voltage, and a gate coupled to receive a third input.

Claim 38

The circuit device of claim 18, further comprising: a second MOSFET having a source-drain path coupled between the emitter of the first bipolar transistor and the second supply voltage terminal, and a gate coupled to receive a third input.

Claim 39

A logic circuit included in a semiconductor device comprising: first and second supply terminals for receiving first and second supply voltages, respectively, a difference voltage between the first and second voltages being equal to or lower than 3.3 volt; an output terminal; an output bipolar transistor having an emitter-collector path coupled between the first supply voltage terminal and the output terminal, and a base, the output bipolar transistor executing one of charging and discharging of a capacitance associated with the output terminal in response to a base driving signal supplied to the base thereof; means coupled between the output terminal and the second supply voltage terminal for executing the other of the charging and discharging of the capacitance; a load circuit coupled between the first supply voltage terminal and the base of the output bipolar transistor; a first bipolar transistor having a collector coupled to the base of the output bipolar transistor, a base coupled to receive a first input, and an emitter; and a first MOSFET having a source-drain path coupled between the emitter of the first bipolar transistor and the second supply voltage terminal, and a gate coupled to receive a second input.

Claim 40

A logic circuit included in a semiconductor device comprising: first and second supply terminals for receiving first and second supply voltages, respectively, a difference voltage between the first and second voltages being equal to or lower than 3.3 volt; an output terminal; an output bipolar transistor having an emitter-collector path coupled between the first supply voltage terminal and the output terminal, and a base, the output bipolar transistor executing one of charging and discharging of a capacitance associated with the output terminal in response to a base driving signal supplied to the base thereof; means coupled between the output terminal and the second supply voltage terminal for executing the other of the charging and discharging of the capacitance; a load circuit coupled between the first supply voltage terminal and the base of the output bipolar transistor; a first bipolar transistor having a collector coupled to the base of the output bipolar transistor, a base coupled to receive a first input, and an emitter; and a first MOSFET having a source-drain path coupled between the emitter of the first bipolar transistor and the second supply voltage terminal, and a gate coupled to receive a second input.

Claim 41

The circuit device of claim 30, wherein the means includes an output MOSFET having a source-drain path coupled between the output terminal and the second supply voltage terminal, and wherein the output MOSFET is turned on when the output bipolar transistor is turned off.

Claim 42

The circuit device of claim 31, wherein the output MOSFET has a gate coupled to the base of the output bipolar transistor.

Claim 43

The circuit device of claim 32, wherein the output bipolar transistor is of an NPN type, and wherein the output MOSFET is of a P-channel type.

Claim 44

The circuit device of claim 31, wherein the load circuit includes a resistance element coupled between the first supply voltage terminal and the base of the output bipolar transistor.

Claim 45

The circuit device of claim 34, wherein the load circuit further includes a level clamping element coupled between the first supply voltage terminal and the base of the output bipolar transistor.

Claim 46

The circuit device of claim 35, wherein said circuit provides an output signal at the output terminal of an ECL level.

Claim 47

The circuit device of claim 30, wherein the output and first bipolar transistors are of an NPN type, and the first MOSFET is of an N-channel type.

Claim 48

The circuit device of claim 30, further comprising: a second MOSFET having a source-drain path coupled between the source-drain path of the first MOSFET and the second supply voltage, and a gate coupled to receive a third input.

Claim 49

The circuit device of claim 30, further comprising: a second MOSFET having a source-drain path coupled between the emitter of the first bipolar transistor and the second supply voltage terminal, and a gate coupled to receive a third input.