Interfering signal rejection circuitry and electronic article surveillance system and method employing same

Claim 2

In combination, in a system for receiving input signals having content of a first frequency of interest in the background of content of a second frequency of interfering nature, and for processing said input signals: (a) first circuit means for providing an identifier signal indicative of said second frequency; (b) second circuit means for receiving said input signals, for delaying said input signals for a time period, and for combining said input signals and such delayed input signals; and (c) third circuit means responsive to said identifier signals for establishing said time period for said second circuit means.

Claim 3

The invention claimed in claim 1 wherein said system includes a transmitter for issuing signals giving rise to such received input signals, and wherein said third circuit means further controls the frequency of transmission of said transmitter responsively to said identifier signals.

Claim 4

The invention claimed in claim 1 wherein said third circuit means includes frequency-control circuitry having an output terminal and first and second input terminals, said first input terminal receiving said identifier signals, said frequency-control circuitry including a first frequency divider connecting said output terminal thereof to said second input terminal thereof.

Claim 5

The invention claimed in claim 3 wherein said first frequency divider has a divider value which is an integral multiple of said second frequency.

Claim 6

The invention claimed in claim 4 wherein said third circuit means further includes a second frequency divider connected to said frequency-control circuitry output terminal and having a divider value for use in establishing said first frequency.

Claim 7

The invention claimed in claim 5 wherein said third circuit means further includes a third frequency divider connected to said frequency-control circuitry output terminal and having a divider value establishing said time period.

Claim 8

The invention claimed in claim 1 wherein said second circuit means includes an analog-to-digital converter (ADC) means for receiving and converting said input signals to provide ADC output signals, memory means for storing said ADC output signals, digital-to-analog converter (DAC) means for receiving and converting signals stored by said memory means and thereby furnished to said DAC means to provide DAC output signals, and control means responsive to signals output by said third circuit means for operating both of said converter means and said memory means.

Claim 9

The invention claimed in claim 7 wherein said control means applies first concurrent control signals to said analog-to-digital converter means and to a write input of said memory means and second concurrent control signals time-spaced from said first concurrent control signals to said digital-to-analog converter means and to a read input of said memory means.

Claim 10

The invention claimed in claim 8 wherein said control means includes counter means incremented by said signals output by said third circuit means and effecting addressing of said memory means for such storing of signals and furnishing of stored signals.

Claim 11

The invention claimed in claim 9 wherein said control means includes reset means connected to said counter means for cycling said counter means.

Claim 12

The invention claimed in claim 10 wherein said second circuit means includes subtractor means receiving said input signals and DAC output signals for effecting said combining to provide said processed signals.

Claim 15

The invention claimed in claim 12 wherein said second circuit means includes frequency-control circuitry having an output terminal and first and second input terminals, said first input terminal receiving said signals indicative of said second frequency, said frequency-control circuitry including a first frequency divider connecting said output terminal thereof to said second input terminal thereof.

Claim 16

The invention claimed in claim 13 wherein said first frequency divider has a divider value which is an integral multiple of said second frequency.

Claim 17

The invention claimed in claim 14 wherein said second circuit means further includes a second frequency divider connected to said frequency-control circuitry output terminal and having a divider value for use in establishing said first frequency.

Claim 18

The invention claimed in claim 15 wherein said second circuit means further includes a third frequency divider connected to said frequency-control circuitry output terminal and having a divider value establishing said time period.

Claim 19

The invention claimed in claim 12 wherein said second circuit means has an output terminal and includes a first frequency divider connected to said output terminal and having a divider value usable in establishing said time period.

Claim 20

The invention claimed in claim 17 wherein said second circuit means includes frequency-control circuitry having said signals indicative of said second frequency as an input thereto.

Claim 21

The invention claimed in claim 18 wherein said frequency-control circuitry has an output terminal and first and second input terminals, said first input terminal receiving said signals indicative of said second frequency, said frequency-control circuitry including a second frequency divider connecting said output terminal thereof to said second input terminal thereof, said output terminal of said frequency-control circuitry being connected to said first frequency divider.

Claim 22

The invention claimed in claim 19 wherein said second frequency divider has a divider value which is an integral multiple of said second frequency.

Claim 23

The invention claimed in claim 20 wherein said second circuit means further includes a third frequency divider connected to said frequency-control circuitry output terminal and having a divider value for use in establishing said first frequency.

Claim 24

The invention claimed in claim 21 wherein said first circuit means includes an analog-to-digital converter (ADC) means for receiving and converting said returned signals to provide ADC output signals, memory means for storing said ADC output signals, digital-to-analog converter (DAC) means for receiving and converting signals stored by said memory means to provide DAC output signals, and control means responsive to signals output by said second circuit means for operating both of said converter means and said memory means.

Claim 25

The invention claimed in claim 22 wherein said control means applies first concurrent control signals to said analog-to-digital converter means and to a write input of said memory means and second concurrent control signals time-spaced from said first concurrent control signals to said digital-to-analog converter means and to a read input of said memory means.

Claim 26

The invention claimed in claim 22 wherein said control means includes counter means incremented by said signals output by said second circuit means and effecting addressing of said memory means for such storing of signals and furnishing of stored signals.

Claim 27

The invention claimed in claim 24 wherein said control means includes reset means connected to said counter means for cycling said counter means.

Claim 28

The invention claimed in claim 22 wherein said first circuit means includes subtractor means receiving said returned signals and DAC output signals for effecting said combining to provide said processed signals.

Claim 29

The invention claimed in claim 22 wherein said second circuit means includes frequency-control circuitry having said signals indicative of said second frequency as an input thereto.

Claim 30

The invention claimed in claim 27 wherein said frequency-control circuitry has an output terminal and first and second input terminals, said first input terminal receiving said signals indicative of said second frequency, said frequency-control circuitry including a first frequency divider connecting said output terminal thereof to said second input terminal thereof.

Claim 31

The invention claimed in claim 28 wherein said first frequency divider has a divider value which is an integral multiple of said second frequency.

Claim 32

The invention claimed in claim 29 wherein said second circuit means further includes a second frequency divider connected to said frequency-control circuitry output terminal and having a divider value for use in establishing said first frequency.

Claim 33

The invention claimed in claim 30 wherein said second circuit means further includes a third frequency divider connected to said frequency-control circuitry output terminal and having a divider value establishing said time period.

Claim 34

In a method for EAS detection of EAS tags by the use of locally available electrical power, the steps of: (a) establishing first signals at a frequency of N, where N is an integral multiple of the frequency of said locally available electrical power; (b) establishing second signals at a frequency of N/M, where M is an integer less than N and transmitting said second signals into a zone to be subjected to EAS detection; (c) receiving signals comprising returns responsive to such transmission in said zone from EAS tags and other objects therein; (d) delaying such received signals by a period related to the period of said locally available electrical power to provide delayed received signals; and (e) combining said received signals with said delayed received signals.

Claim 35

In a method for EAS detection of EAS tags by the use of locally available electrical power, the steps of: (a) establishing first signals at a frequency of N, where N is an integral multiple of the frequency of said locally available electrical power; (b) establishing second signals at a frequency of N/M, where M is an integer less than N and transmitting said second signals into a zone to be subjected to EAS detection; (c) receiving signals comprising returns responsive to such transmission in said zone from EAS tags and other objects therein; (d) delaying such received signals by a period related to the period of said locally available electrical power to provide delayed received signals; and (e) combining said received signals with said delayed received signals.

Claim 36

In a method for EAS detection of EAS tags by the use of locally available electrical power to effect signal transmission into a controlled zone, the steps of: (a) interrelating the frequency of the transmitted signals to the local power frequency in predetermined manner; (b) receiving signals returned from EAS tags and other objects in said zone responsively to the transmitted signals; (c) processing such received signals by delaying the same by a time delay related to said local power frequency and combining received signals and delayed received signals.

Claim 37

In a method for EAS detection of EAS tags by the use of locally available electrical power to effect signal transmission into a controlled zone, the steps of: (a) interrelating the frequency of the transmitted signals to the local power frequency in predetermined manner; (b) receiving signals returned from EAS tags and other objects in said zone responsively to the transmitted signals; (c) processing such received signals by delaying the same by a time delay related to said local power frequency and combining received signals and delayed received signals.

Claim 38

The invention claimed in claim 33 wherein said step (a) is practiced in part by effecting a frequency domain asynchronism as between selected harmonics of said frequency of the transmitted signals and said local power frequency.

Claim 39

The invention claimed in claim 34 wherein said step (b) is practiced in part by effecting a time domain synchronism as between received signals and said local power frequency.

Claim 40

The invention claimed in claim 33 wherein said step (b) is practiced in part by effecting a time domain synchronism as between received signals and said local power frequency.

Claim 41

In combination: (a) a system for processing signals returned from objects in the vicinity of a controlled zone responsively to incidence thereon of signals transmitted therein at a first frequency by a transmitter supplied with local power at a second frequency, said system comprising: (1) first circuit means for receiving such returned signals, delaying said returned signals for a time period, and combining said returned signals and such delayed returned signals to provide such processed signals: (2) second circuit means responsive to signals indicative of said second frequency for establishing both said time period for said first circuitry and said first frequency for said transmitter; (b) receiver means for receiving said processed signals and for examining the same for harmonic content related to said first frequency and generating an alarm activating output signal upon detection of preselected such harmonic content in said processed signals; and (c) alarm means responsive to said alarm activating output signal to provide alarm indication.

Claim 42

In combination: (a) a system for processing signals returned from objects in the vicinity of a controlled zone responsively to incidence thereon of signals transmitted therein at a first frequency by a transmitter supplied with local power at a second frequency, said system comprising: (1) first circuit means for receiving such returned signals, delaying said returned signals for a time period, and combining said returned signals and such delayed returned signals to provide such processed signals: (2) second circuit means responsive to signals indicative of said second frequency for establishing both said time period for said first circuitry and said first frequency for said transmitter; (b) receiver means for receiving said processed signals and for examining the same for harmonic content related to said first frequency and generating an alarm activating output signal upon detection of preselected such harmonic content in said processed signals; and (c) alarm means responsive to said alarm activating output signal to provide alarm indication.

Claim 43

The invention claimed in claim 37 wherein said second circuit means includes frequency-control circuitry having said signals indicative of said second frequency as an input thereto.

Claim 44

The invention claimed in claim 38 wherein said frequency-control circuitry has an output terminal and first and second input terminals, said first input terminal receiving said signals indicative of said second frequency, said frequency-control circuitry including a first frequency divider connecting said output terminal thereof to said second input terminal thereof.

Claim 45

The invention claimed in claim 39 wherein said first frequency divider has a divider value which is an integral multiple of said second frequency.

Claim 46

The invention claimed in claim 40 wherein said second circuit means further includes a second frequency divider connected to said frequency-control circuitry output terminal and having a divider value for use in establishing said first frequency.

Claim 47

The invention claimed in claim 41 wherein said second circuit means further includes a third frequency divider connected to said frequency-control circuitry output terminal and having a divider value establishing said time period.

Claim 52

The invention claimed in claim 44 wherein said step (a) is practiced in part by effecting a frequency domain asynchronism as between selected harmonics of said frequency of the transmitted signals and said local power frequency.

Claim 53

The invention claimed in claim 45 wherein said step (b) is practiced in part by effecting a time domain synchronism as between received signals and said local power frequency.

Claim 54

The invention claimed in claim 44 wherein said step (b) is practiced in part by effecting a time domain synchronism as between received signals and said local power frequency.