Digital IC-microcomputer interface

Claim 2

In a communication and control network, the combination of a digital IC coupled to a common communication line of said network and adapted to receive plural bit messages which are modulated on a carrier signal and asynchronously transmitted over said line from a central controller, a serial shift register in said device having a data input and a clock input, means for loading the message bits of a received message into said register through said data input thereof, a microcomputer interfaced with said device over a serial data line and a serial clock line, and means in said device and responsive to the reception of a message from said central controller which includes an enable interface instruction for connecting said serial clock line to said clock input of said serial shift register and preventing a subsequent message from being supplied to said data input of said serial shift register.

Claim 3

The combination of claim 1, which includes a digital demodulator in said device having an output normally connected to said data input and said clock input of said serial shift register, and means in said device responsive to the reception of said message for disconnecting said demodulator output from said data input of said serial shift register.

Claim 4

The combination of claim 2, wherein said microcomputer interface includes a read-write line, and means in said device and responsive to a predetermined signal on said read-write line for restoring said normal connection of said digital demodulator to said data input and said clock input of said serial shift register.

Claim 5

The combination of claim 3, wherein said predetermined signal comprises successive low and high signals on said read-write line.

Claim 6

The combination of claim 4, which includes means in said device for producing a control signal in response to said successive low and high signals on said read-write line, and means responsive to said control signal for restoring said normal connection of said digital demodulator to said data input and said clock input of said serial shift register.

Claim 7

In a communication and control network, the combination of a digital IC device coupled to a common network line and adapted to receive and store in a serial shift register in said device plural bit messages which are modulated on a carrier signal and asynchronously transmitted over said line from a central controller, means in said device and responsive to the storage of a message in said shift register which includes an enable interface instruction for establishing an interface to an associated microcomputer whereby said microcomputer can read the message bits stored in said device, and means in said device and responsive to said enable interface instruction for preventing a subsequent message transmitted over said line from being stored in said serial shift register.

Claim 8

In a communication and control network, the combination of a digital IC device coupled to a common network line and adapted to receive and store in a serial shift register in said device plural bit messages which are modulated on a carrier signal and asynchronously transmitted over said line from a central controller, means in said device and responsive to the storage of a message in said shift register which includes an enable interface instruction for establishing an interface to an associated microcomputer whereby said microcomputer can read the message bits stored in said device, and means in said device and responsive to said enable interface instruction for preventing a subsequent message transmitted over said line from being stored in said serial shift register.

Claim 9

The combination of claim 6, which includes means in said device for continuing to prevent the storage of messages in said serial shift register which are transmitted over said line until reception of a predetermined signal from said microcomputer over said interface.

Claim 10

The combination of claim 7, which includes means in said device and responsive to said predetermined signal for enabling said device to store in said serial shift register subsequent messages which are transmitted over said line.

Claim 11

The combination of claim 6, which includes means in said device for storing in said serial shift register data transmitted to said device from said microcomputer over said interface, and means in said device for transmitting the microcomputer data stored in said serial shift register onto said common line as a modulated carrier network message.

Claim 12

The combination of claim 9, wherein transmission of said microcomputer data is initiated in response to a control signal generated by said microcomputer and supplied to said device over said interface.

Claim 13

The combination of claim 10 which includes means in said device and responsive to said control signal for enabling said serial shift register to store a subsequent message transmitted over said network line.

Claim 14

The combination of claim 6, wherein said interface includes a busy line, and means in said device for supplying a receive busy signal to said busy line whenever a message is received from said common network line, thereby to inform said microcomputer of the transmission of said message.

Claim 15

The combination of claim 12, wherein said busy signal has a duration corresponding to the length of said message transmitted over said common network line.

Claim 16

The combination of claim 12, which includes means in said device for storing in said serial shift register data transmitted to said device over said interface, and means in said device for transmitting the microcomputer data stored in said serial shift register onto said common line as a modulated carrier network message.

Claim 17

The combination of claim 14, which includes means in said device for supplying a transmission busy signal to said busy line when said transmission of microcomputer data onto said common line is initiated.

Claim 18

The combination of claim 15, wherein said transmission busy signal has a duration corresponding to the length of said microcomputer data transmitted message.

Claim 19

In a communication and control system, the combination of a digital IC device connected to a communication network link and adapted to receive plural bit messages which are modulated on a carrier signal and asynchronously transmitted over said link from a central controller, a serial shift register in said device having a data input and a clock input, means in said device for storing the bits of a received message in said register, a microcomputer interfaced to a busy line, means in said device for connecting the output of said serial shift register to said serial data line; means in said device for connecting said serial clock line to said clock input of said serial shift register, means in said microcomputer for reading the message bits stored in said register by applying successive clock pulses to said serial clock line to shift successive stored bits onto said serial data line and successively reading said serial data line, and means in said device responsive to one of said plural bit messages for producing a receive busy signal on said busy line which has a duration corresponding to the time said device is receiving a message from said network link, said means in said microprocessor for reading the message bits stored in said register operating to read said serial data line only in the absence of said receive busy signal.

Claim 20

In a communication and control system, the combination of a digital IC device connected to a communication network link and adapted to receive plural bit messages which are modulated on a carrier signal and asynchronously transmitted over said link from a central controller, a serial shift register in said device having a data input and a clock input, means in said device for storing the bits of a received message in said register, a microcomputer interfaced to a busy line, means in said device for connecting the output of said serial shift register to said serial data line; means in said device for connecting said serial clock line to said clock input of said serial shift register, means in said microcomputer for reading the message bits stored in said register by applying successive clock pulses to said serial clock line to shift successive stored bits onto said serial data line and successively reading said serial data line, and means in said device responsive to one of said plural bit messages for producing a receive busy signal on said busy line which has a duration corresponding to the time said device is receiving a message from said network link, said means in said microprocessor for reading the message bits stored in said register operating to read said serial data line only in the absence of said receive busy signal.

Claim 21

The combination of claim 17, which includes means in said device for transmitting a modulated carrier message onto said network link which includes data stored in said serial shift register, and means in said device for producing a transmit busy signal on said busy line which has a duration corresponding to the time said device is transmitting said message.

Claim 22

The combination of claim 18, wherein said digital IC has a busy output terminal, and means in said device for supplying either said receive busy signal or said transmit busy signal to said output terminal.