US4972500A
Expired / Lapsed
US
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Image density processor
Assignee: Canon Inc
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Filing: 1989-06-27
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Granted: 1990-11-20
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Expires: 2009-06-27
Abstract
Abstract There is an image processing apparatus which can further digitally control the density of the image signal read out from the image file in which the dither-processed image signal was stored. This apparatus comprises an input device to input the dither-processed image signal, table memories which output the density correction data using the image signal of a plurality of bits inputted by the input device as an input address, and a visible output device to output the outputs of the table memories as visible outputs, wherein the input device reads out the dither-processed image signal from the image file.
Inventors
- 👤 Hiroaki Ishii
- 👤 Katsunori Kato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:08
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/40; H04N1/40075
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
132 words
An image processing apparatus comprising: input means for inputting a plurality of bi-level image signals of a predetermined plural number of bits each corresponding to a respective portion of a predetermined area, the bi-level image signals having been binarization-processed; a table memory comprising a conversion table using the bi-level image signals as multi-bit input addresses, for correcting density of the input bi-level image signals by changing a number of pixels to be visualized in the predetermined area and for outputting a plurality of density-corrected bi-level image signals having a number of bits equal to the predetermined number of bits; and visible-output means for outputting an output of said table memory as a visible output, wherein, in said table memory, a plurality of conversion tables are provided according to a density correction amount.
Claim 2
Dependent Claim
132 words
An image processing apparatus comprising: input means for inputting a plurality of bi-level image signals of a predetermined plural number of bits each corresponding to a respective portion of a predetermined area, the bi-level image signals having been binarization-processed; a table memory comprising a conversion table using the bi-level image signals as multi-bit input addresses, for correcting density of the input bi-level image signals by changing a number of pixels to be visualized in the predetermined area and for outputting a plurality of density-corrected bi-level image signals having a number of bits equal to the predetermined number of bits; and visible-output means for outputting an output of said table memory as a visible output, wherein, in said table memory, a plurality of conversion tables are provided according to a density correction amount.
Claim 3
Dependent Claim
35 words
An image processing apparatus according to claim 1, which further comprises storage means for storing the binarization-processed image signals, and in which said input means reads out said binarization-processed image signals from said storage means.
Claim 4
Dependent Claim
39 words
An image processing apparatus according to claim 1, wherein said table memory has a number of input address bits equal to a number of threshold values which have been used in the binarization process of the binarization-processed image signal.
Claim 5
Dependent Claim
44 words
An image processing apparatus according to claim 1, wherein, more specifically, said input means is structured and arranged for inputting, as the bi-level image signal, a bi-level image signal which has been subjected to binarization-processed including a dither processing, with respect to one pixel.
Claim 6
Dependent Claim
43 words
An image processing apparatus according to claim 4, wherein, more specifically, said conversion table is structured and arranged to use, as the bi-level image signal used as a multi-bit input address, a signal determined in accordance with a pattern of the dither processing.
Claim 7
Dependent Claim
85 words
An image processing apparatus comprising: input means for inputting a plurality of bi-level image signals each corresponding to a respective pixel in a multi-pixel block, each of the bi-level image signals being one which has been binarization-processed; and output means for making changeable, for each block, a number of pixels to be visualized in said block so as to make a density of the block changeable, and for outputting the plurality of bi-level image signals after processing to make the density of the block changeable.
Claim 8
Dependent Claim
85 words
An image processing apparatus comprising: input means for inputting a plurality of bi-level image signals each corresponding to a respective pixel in a multi-pixel block, each of the bi-level image signals being one which has been binarization-processed; and output means for making changeable, for each block, a number of pixels to be visualized in said block so as to make a density of the block changeable, and for outputting the plurality of bi-level image signals after processing to make the density of the block changeable.
Claim 9
Dependent Claim
31 words
An apparatus according to claim 6, further comprising storage means for storing the binarization-processed image signal, and wherein said input means reads out the binarization-processed image signal from said storage means.
Claim 10
Dependent Claim
34 words
An apparatus according to claim 6, wherein, more specifically, said input means is for inputting, as the bi-level image signal, a bi-level image signal which has been subjected to binarization-processing including a dither processing.
Claim 11
Dependent Claim
36 words
An apparatus according to claim 6, wherein said output means includes a table memory which outputs the plurality of level-changed bi-level image signals by using the input bi-level image signal of each pixel as an address.
Claim 12
Dependent Claim
23 words
An apparatus according to claim 6, further comprising visible-output means for visibly outputting the level-changed bi-level image signals output by said output means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-19 | 1994-05-21 | 1994-11-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-19 | 1998-05-21 | 1998-11-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-19 | 2002-05-21 | 2002-11-20 | $7700.00 | Window Closed / Lapsed |